### CS223 : Hardware Lab

#### Instructor: Dr. A. Sahu

Course Structure:
• Combinational Circuit and Sequential Circuit Design .
• Data path design using ICs and bread board Ex load/store operation, ALU operation, multiplier;
• Instruction interpretation: micro-operations and their RTL specification. CPU design: Hardwired and Micro-programmed.

Group structure of CS223 Group Structure
VHDL Tutorial http://esd.cs.ucr.edu/labs/tutorial/
Book VHDL Programming by Prerry
Some Free HDL Simulator: GNU HDL Simulator, Command line Linux type in Windows
Free HDL Simulator:Simli Simulator (Open Sonata, Create project, add vhdl file, simulate)
Some Hardware Modeling Tutorial from IIT Delhi 02-HWModelling.pdf and 03-VHDL.pdf
Assignments
1. Experiment 1: (6 Hour) Combinational Circuit/Logic minimization and Sequential Circuit

(a) Design a Combinational circuit with 4 input (BCD) and 7 output to interface/drive a 7 segment display.
Use logic optimization and minimization to realize this 7 segment driver. You are not allowed to 74LS47/48 decoder. Draw a need diagram of your circuit to realize this functions.

(b) Design a JK Flip‐Flop, Edge triggered J‐K NAND Flip Flop and show its functionality Handle race condition and clock gating in your circuit.

2. Experiment 2: (15 Hour) Data path design using ICs and bread board Ex load/store operation, ALU operation, multiplier;
Assignment to be do using IC Components like Adder/ALU, MUX, Memory, Decoder to implement Operations on two number from memory to store the result in memory. Operations are add, subtract and multiply.

Part (A) (6 hour ) Design a 32 bit ALU using a Carry Skip Adder/Carry Look Ahead adder. Calculate the Delay of adder, simulate your design using any HDL simulator. Basic ALU perform 3 operations Add/Subtract/Compare (if possible multiply). Here you have to design 32 bit carry skip adder/carry look ahead adder.
This parts of assignment is to design in Pen/Paper, HDL and Simulate HDL on some HDL simulator like ModelSim or Simuli or GHDL.

Part B: (9 Hour) Design a 4 bit data path for CPU to perform ADD/SUB/MUL/CMP operations (a) Multiplier using addition method (AxB=A+A+A… B times). You can use B a parallel down counter, C as a counter and A and D are Registers

(b) Design to read two number from memory, do operation specified you and store it back to memory. Use concepts form part A to create 4 bit ALU. Memory operations are Read/Write but before that we have place Address in MAR ( Memory Address Reg) and Data in MDR buffer (Memory Data Register)

3. Experiment 3: (21 Hour) Extension of Assignment 2 to add control path to make a CPU using either Hardware/micro-prograamed;
Detail of assignment 4
As EEPROM Programmer and some EEPROM are not working, use one RAM chip to both control memory and program memory
Using one RAM design will be easier but not recommended
Download program from PC to board using parallel port programming

Books : Text:
1. Patterson, D.A., and Hennessy, J.L. , “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann Publishers, 4th Edition, Inc.2005

Lab Class timing, Venue and Rules
• Venue: Hardware Lab
• Timing : Slot AL1 { MON:2PM–5PM }