Chandan Karfa

Associate Professor, Department of CSE
IIT Guwahati, Guwahati - 781039
Assam, India

Office

Room No.: H-002
Phone: +91 361 2582375
Email: ckarfa @ iitg.ac.in

Personal Webpage: Click here to visit.

Education

PhD
Formal Verification of Behavioural Transformations, Department of Computer Science and Engineering, IIT Kharagpur, 2011.

MS (by Research)
Formal Verification of High-level Synthesis, Department of Computer Science and Engineering, IIT Kharagpur, 2007.

B.Tech (IT)
Information Technology, University of Kalyani, West Bangal, 2004.

Work Experiences

Visiting Researcher
New York University, May 2019 - July 2019.

Senior R&D Engineer
Synopsys (India) Pvt. Ltd, September 2011 - July 2016.

Research Interests

Formal Verification, High-level Synthesis, Electronic Design Automation, Hardware Security, Verification of Compiler Optimizations.

Primary Research Group

Computer Architecture and Embedded Systems

Secondary Research Group(s)

Theoretical Computer Science

Courses Offered

2021-2022 ⋄ Even Semester ⋄ CS577 : C-Based VLSI Design: Synthesis, Optimization and Verification
2021-2022 ⋄ Odd Semester ⋄ CS221 : Digital Design
2021-2022 ⋄ Odd Semester ⋄ CS101 : Introduction To Computing
2020-2021 ⋄ Even Semester ⋄ CS577 : C-Based VLSI Design: Synthesis, Optimization and Verification
2020-2021 ⋄ Odd Semester ⋄ CS221 : Digital Design
2019-2020 ⋄ Even Semester ⋄ CS577 : C-Based VLSI Design: Synthesis, Optimization and Verification
2019-2020 ⋄ Odd Semester ⋄ CS591H :
2019-2020 ⋄ Odd Semester ⋄ CS593 :
2019-2020 ⋄ Odd Semester ⋄ CS513 : Data Structures Lab
2018-2019 ⋄ Even Semester ⋄ CS577 : C-Based VLSI Design: Synthesis, Optimization and Verification
2018-2019 ⋄ Odd Semester ⋄ CS210 : Data Structure Laboratory
2018-2019 ⋄ Odd Semester ⋄ CS201 : Discrete Mathematics
2017-2018 ⋄ Odd Semester ⋄ CS210 : Data Structure Laboratory
2017-2018 ⋄ Odd Semester ⋄ CS201 : Discrete Mathematics
2017-2018 ⋄ Odd Semester ⋄ CS526 : Cad For Vlsi
2016-2017 ⋄ Even Semester ⋄ CS526 : Cad For Vlsi
2016-2017 ⋄ Even Semester ⋄ CS223 : Computer Architecture and Organization
2016-2017 ⋄ Odd Semester ⋄ CS201 : Discrete Mathematics
2016-2017 ⋄ Odd Semester ⋄ CS210 : Data Structure Laboratory

Ph.D. Students continuing

NILOTPOLA SARMA
PRIYANKA PANIGRAHI
DEBABRATA SENAPATI
Adem Mohammed Abderehman
Cherinet Kejela Addise

M.Tech. Students Ongoing

CHINMAY RATHOD
VAISHALI GHANSHYAM CHAUDHARI
KARTHIK MADDALA
ANUJ SINGH THAKUR
Jatin Gupta
SUBHAM DAS

Ph.D. Students Completed

Supervisors: Chandan Karfa, Santosh Biswas ⋄ Scholar Name: Surajit Das ⋄ Thesis Title: Formal Modeling of Network -on -Chip and its Application in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms.
Supervisors: Chandan Karfa, Arnab Sarkar ⋄ Scholar Name: Sanjit Kumar Roy ⋄ Thesis Title: Task and Message Co-scheduling Strategies in Real-time Cyber-Physical Systems.
Supervisor: Chandan Karfa ⋄ Scholar Name: Ramanuj Chouksey ⋄ Thesis Title: Formal Verification and Security Analysis of High-level Synthesis.

M.Tech. Students Completed

Supervisor: Chandan Karfa ⋄ Scholar Name: Divyanshu Nauni ⋄ Thesis Title: "Analyzing Area and Latency overhead in C and RTL-locked designs"
Supervisor: Chandan Karfa ⋄ Scholar Name: Rittick Mondal ⋄ Thesis Title: "Scalable SMT Attack on Higher Level Logic Locking"
Supervisor: Chandan Karfa ⋄ Scholar Name: Prosenjit Biswas ⋄ Thesis Title: "C TO RTL EQUIVALENCE CHECKING"
Supervisor: Chandan Karfa ⋄ Scholar Name: NAVJOT SINGH ⋄ Thesis Title: "Logic locking against scan chain attacks"
Supervisor: Chandan Karfa ⋄ Scholar Name: MUKUL CHATURVEDI ⋄ Thesis Title: "Verication of Dataflow Optimization in Array-Intensive Programs"
Supervisor: Chandan Karfa ⋄ Scholar Name: ABHIK PAUL ⋄ Thesis Title: "Information Leakage Analysis of Compiler Optimizations"
Supervisors: Chandan Karfa, ⋄ Scholar Name: GAGAN GAYARI ⋄ Thesis Title: "Genetic Algorithm based attack on Register Transfer Level Locking"
Supervisor: Chandan Karfa ⋄ Scholar Name: RUPAK GUPTA ⋄ Thesis Title: "Hardware Trojan Detection in High-level Synthesis Generated RTLs"
Supervisor: Chandan Karfa ⋄ Scholar Name: JAYPRAKASH PATIDAR ⋄ Thesis Title: "An RTL-to-C Reverse Engineering based Fast Simulation Framework for High-level Synthesis"
Supervisor: Chandan Karfa ⋄ Scholar Name: ARSHDEEP KAUR ⋄ Thesis Title: "Approach for Checking Robustness of Gate -level Logic Locking."
Supervisor: Chandan Karfa ⋄ Scholar Name: YOM NIGAM ⋄ Thesis Title: "Register Transfer Level Logic Obfuscation"
Supervisor: Chandan Karfa ⋄ Scholar Name: OZA JAY MUKESHKUMAR ⋄ Thesis Title: "A Fast Simulation Framework for High-level synthesis"
Supervisor: Chandan Karfa ⋄ Scholar Name: PANKAJ KUMAR KALITA ⋄ Thesis Title: "Inverse Operation Detection and Counter Example Generation during Path Based Equivalence Checking"

Publications

Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa, "SRIL: Securing Registers from Information Leakage at Register Transfer Level", 37th International Conference of VLSI Design (VLSID 2024), 2024, February, 2024
Praveen Karmakar, Divyandhu Nauni, Chandan Karfa, "Analyzing Area and Latency Overhead in C and RTL Locked Designs", IEEE Asia Pacific Conference On Circuits And Systems (APCCAS 2023), October, 2023
Debabrata Senapati, Kaushik Rajesh, Arnab Sarkar, Chandan Karfa, "TMDS: A Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems", "ACM Transactions on Design Automation of Electronic Systems", 28, 16, October, 2023
Priyanka Panigrahi, Chandan Karfa, "An Investigation into the Security of Register Allocation with Spilling and Splitting", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 300-305, September, 2023
Priyanka Panigrahi, Chandan Karfa, "Translation Validation of Information Leakage of Compiler Optimizations", "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", 42, 3585 - 3598, April, 2023
Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Peddaiahgari Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati, "RTL Simulation Acceleration with Machine Learning Models", ISQED 2024, February, 2023
Praveen Karmakar, Marpina Bharani, Chandan Karfa, "Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction", in 37th International Conference of VLSI Design (VLSID 2024), 2024, February, 2023
Debabrata Senapati, Arnab Sarkar, Dharmendra Maurya, Chandan Karfa, "ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems", 37th International Conference of VLSI Design (VLSID 2024), 2024., February, 2023
Debabrata Senapati, Arnab Sarkar, Chandan Karfa, "Energy-aware Real-time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems", " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", December, 2022
Mohammed Abderehman, Rupak Gupta, Rakesh Reddy Theegala, Chandan Karfa, "BLAST: Belling the Black-Hat High-Level Synthesis Tool", "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", 41, 3661-3672, October, 2022
Priyanka Panigrahi, Abhik Paul, Chandan Karfa, "Quantifying Information Leakage for Security Verification of Compiler Optimizations", " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", 41, 4385-4396, August, 2022
Surajit Das, Chandan Karfa, Santosh Biswas, "Accelerating NoC Verification Using a Complete Model and Active Window", "IEEE Access", 10, 88985-88999, August, 2022
Mohammed Abderehman, Rakesh Theegala Reddy, Chandan Karfa, "DEEQ: Data-driven End-to-End Equivalence Checking of High-level Synthesis", ISQED 2022, April, 2022
Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay, "Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking", ISQED 2022, April, 2022
Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, Prabhat Mishra, "Secure Register Allocation for Trusted Code Generation", "IEEE Embedded Systems Letters", January, 2022
S. Das, C. Karfa, "Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC", "EEE Embedded Systems Letters", September, 2021
D. Senapati, A. Sarkar, C. Karfa, "HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems", "ACM Transactions on Embedded Computing Systems (TECS), (Special Issue on ESWEEK 2021)", July, 2021
S. Das, C. Karfa, "Formal Modeling and Verification of Starvation-Freedom in NoCs", 10th International Symposium on Embedded Computing and System Design (ISED), July, 2021
S. Das, C. Karfa, "Deadlock Avoidance in Torus NoC Applying Controlled Move via Wraparound Channels", 10th International Symposium on Embedded Computing and System Design (ISED), July, 2021
M. Abderrahman, R. Gupta, C. Karfa, "Reverse Engineering Register to Variable Mapping in High-Level Synthesis", IEEE Computer Society Annual Symposium on VLSI, (ISVLSI), July, 2021
D. Senapati, A. Sarkar, C. Karfa, "HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems", ACM SIGBED International Conference on Embedded Software (EMSOFT), July, 2021
M. Abderrahman, J. Patidar, J. Oza, Y. Nigam, T. M. AbdulKhader, C. Karfa, "FastSim: A Fast Simulation Framework for High-Level Synthesis", "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", June, 2021
Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey and Ramesh Karri, "HOST: HLS Obfuscations against SMT Attack", DATE 2021, March, 2021
D. Senapati, A. Sarkar and C. Karfa, "PRESTO: A Penalty-aware Real-time Scheduler for Task Graphs on Heterogeneous Platforms", "IEEE Transactions on Computers", December, 2020
Melbin John, Aadil Hoda, Ramanuj Chouksey and Chandan Karfa, "SAT Based Partial Attack on Compound Logic Locking", IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), December, 2020
S. Maddheshiya, R. Chouksey and C. Karfa, "VP_TT: A Value Propagation Based Equivalence Checker for Testability Transformations", "IET Software", October, 2020
Pankaj Kalita, Ramanuj Chouksey and Chandan Karfa, "Automatic Inverse Operation Detection and its Impact in High-level Synthesis", 24th International Symposium on VLSI Design and Test (VDAT 2020), August, 2020
R. Chouksey, C. Karfa, "Verification of Scheduling of Conditional Behaviors in High-level Synthesis", "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", 8, 1638-1651, July, 2020
Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg and Ramesh Karri, "Is Register Transfer Level Locking Secure Against SAT Attacks?", Design, Automation and Test in Europe Conference & Exhibition (DATE), 550-555, March, 2020
Surajit Das, Chandan Karfa, Santosh Biswas, "Formal Modeling of Network-on-Chip Using CFSM and Its Application in Detecting Deadlock", "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", 28, 1016 - 1029, January, 2020
C. Karfa, D. Sarkar, C. Mandal, "Verification of parallelising transformations of KPN models", "IET Cyber-Physical Systems: Theory & Applications", 4, 276 - 289, October, 2019
R. Chouksey, C. Karfa, K. Banerjee, P. K. Kalita and P. Bhaduri, "Counter-example generation procedure for path-based equivalence checkers", "IET Software", 13, 280-285, August, Link, 2019
Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, "Formal Verification of Optimizing Transformations during High-level Synthesis", ISEC 2019, 27:1-27:5, February, Link, 2019
Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri , "Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples", 32nd International Conference on VLSI Design 2019, 377-382, January, Link, 2019
Priyanka Panigrahi, Rajesh Kumar Jha and Chandan Karfa, "User Guided Register Manipulation in Digital Circuits", 23rd VLSI Design and Test Symposium (VDAT 2019), 2019
Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, "Translation Validation of Code Motion Transformations Involving Loops", "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", June, Link, 2018
Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa and Pankaj Kumar Kalita, "Automatic Detection of Inverse Operations while Avoiding Loop Unrolling", 40th International Conference on Software Engineering (ICSE 18), May, 2018
Kunal Banerjee and Chandan Karfa, "Compiler-agnostic Translation Validation", Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, February, 2018
R. Chouksey, C. Karfa and P. Bhaduri, "Translation Validation of Loop Invariant Code Optimizations Involving False Computations", 21st International Symposium on VLSI Design and Test (VDAT 2017), 767-778, July, Link, 2017
Surajit Das, Chandan Karfa and Santosh Biswas, "xMAS Based Accurate Modeling and Progress Verification of NoCs", VLSI Design and Test - 21st International Symposium, VDAT 2017, 792-804, July, 2017
C. Karfa, "Replication Strategies for FPGAs", Synopsys India Technical Conference 2016, 2016
C. Karfa, "Automatic Register Balancing in Model-based High-level Synthesis", 6th Asia Symposium on Quality Electronic Design (ASQED 2015), 43-49, 2015
K. Banerjee, C. Karfa, D. Sarkar, C Mandal, "Verification of Code Motion Techniques using Value Propagation", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 33, 1180-1193, 2014
C. Karfa, S. Jain, "On Multi-cycle Path Support in Model based High-level Synthesis", IEEE Students Technology Symposium 2014, 253-258, 2014
C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Verification of loop and arithmetic transformations of array-intensive behaviors", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 32, 1787-1800, 2013
C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Experimentation with SMT Solvers and Theorem Provers for Verification of Loop and Arithmetic Transformations", 5th IBM Collaborative Academia Research Exchange (I-CARE 2013), 3:1-3:4, 2013
C. Karfa, D. Sarkar, C Mandal, "Verification of KPN level transformation", 26th International Conference on VLSI Design (VLSID) 2013, 338-343, 2013
C. Karfa, D. Sarkar, C Mandal, "Formal Verification of Code Motion Techniques using Data-flow Driven Equivalence Checking", "ACM Transactions on Design Automation of Electronic Systems", 17, 30:1--30:37, 2012
C. Karfa, "Application of Behavioural Transformations in Embedded System Design", "IETE Technical Review", 29, 372-379, 2012
C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques", IEEE International Symposium on Electronic System Design (ISED) 2012, 67-71, 2012
C. Karfa, D. Sarkar, C Mandal, "Verification of Register Transfer Level Low Power Transformations", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, 313-314, 2011
C. Karfa, D. Sarkar, C Mandal, "Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 29, 479-492, 2010
C. Karfa, D. Sarkar, C Mandal, "Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2010, 428-433, 2010
C. Karfa, D. Sarkar, C Mandal, P. Kumar, "An Equivalence Checking Method for Scheduling Verification in High-level Synthesis", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 27, 556-569, 2008
C. Karfa, D. Sarkar, C Mandal, "Verification of Data-path and Controller Generation Phase in High-level Synthesis", 15th IEEE International Conference on Advanced Computing and Communication (ADCOM 2007), 315-320, 2007
C. Karfa, D. Sarkar and C Mandal, "Hand-in-hand Verification of High-level Synthesis", ACM Great Lakes Symposium on VLSI 2007, 429-434, 2007
C. Karfa, C. Mandal, D. Sarkar, C. Reade, "Register Sharing Verification during Data-path Synthesis", IEEE International Conference on Computing: Theory and Application 2007, 135-140, 2007
S. Biswas, C. Karfa, H. Kanwar, D.Sarkar, S. Mukhopadhyay A. Patra, "Fairness of Transitions in Diagnosability Analysis of Hybrid Systems", American Control Conference, 2006, 2664-2669, July, 2006
C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade, "A Formal Verification Method of Scheduling in High-level Synthesis", IEEE International Symposium on Quality Electronic Design 2006, 71-76, 2006
C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade, "Verification of Scheduling in High-level Synthesis", IEEE Computer Society Annual Symposium on VLSI 2006, 141-146, 2006
C. Karfa, J. S. Reddy, S. Biswas, C. R. Mandal, D. Sarkar, "SAST An Interconnection aware high level synthesis tool", VLSI Design and Test (VDAT 2005), 285-293, 2005
C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Equivalence Checking of Array-Intensive Programs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, 156-161

Recognitions

Qualcomm Faculty Award 2021
TechInventor Award 2013, India Electronics and Semiconductor Association (IESA)
Innovative Student Projects Award 2013 (Doctoral Level), Indian National Academy of Engineering (INAE)
Best Paper Award, 5th IBM Collaborative Academia Research Exchange 2013
2nd Runner-up TechVista 2010, Microsoft Research India annual research symposium
Winner of EDA software contest, 22nd international conference on VLSI design and embedded systems 2009
Microsoft Research India PhD Fellowship 2008-2012, Microsoft Research India
Innovative Student Projects Award 2008 (Master Level), Indian National Academy of Engineering (INAE)
Best Paper Award, ADCOM 2007