Research Papers in conferences

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  1. 1. P. K. Manchi, R. Paily and A. K. Gogoi, "Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 581-582. doi: 10.1109/VLSID.2016.19

  2. 2. V. C. Sekhar, S. Bora, M. Das, P. K. Manchi, S. Josephine and R. Paily, "Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 421-426. doi: 10.1109/VLSID.2016.11

  3. 3. S. Mondal and R. P. Paily, "An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 224-229. doi: 10.1109/VLSID.2016.79

  4. 4. Satyabrata Dash, Deepak Joshi, Gaurav Trivedi, "CMOS Analog Circuit Optimization via River Formation Dynamics," IEEE 26th International Conference on Radioelektronika, Slovak Republic, 2016. (Best Paper Award)

  5. 5. Satyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi, "Applying River Formation Dynamics to Analyze VLSI Power Grid Networks," IEEE 29th International Conference on VLSI Design, Kolkata, 2016. (Honorable Mention Award)

  6. 6. Vishnuram Abhinav, Dheeraj Kumar Sinha, Amitabh Chatterjee and Forrest Brewer, "A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach", 29th International Conference on VLSI Design (2016), Kolkata.

  7. 7. Dheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav, Gaurav Trivedi and Victor Koldyaev, "A Novel Capacitorless DRAM Cell Design using Band-gap Engineered Junctionless Double-gate FET", 29th International Conference on VLSI Design (2016), Kolkata.

  8. 8. Dheeraj Kumar Sinha, Amitabh Chatterjee, Gaurav Trivedi and Victor Koldyaev, "Design of Band-gap Engineered Silicon-Germanium Junctionless Double-gate FET for ZRAM application," 6th International Conference on Computers and Devices for Communication (CODEC 2015), Kolkata.

  9. 9. Dheeraj Kumar Sinha, Amitabh Chatterjee, Gaurav Trivedi and Victor Koldyaev, "Analysis and Design of ZRAM Cell for Low Voltage Operations," 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015), Bangalore.

  10. 10. Dheeraj Kumar Sinha, Amitabh Chatterjee and Gaurav Trivedi, "Two Dimensional Numerical Simulator for Modeling NDC Region in SNDC Devices", XXVII IUPAP Conference on Computational Physics (CCP 2015), Guwahati.

  11. 11. Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha and Rajan Singh, "Methodology for optimizing ESD protection for high speed LVDS based I/Os", 19th International Symposium on VLSI Design and Test (VDAT), Ahmedabad.

  12. 12. Saurav Roy, Shiva Puri Goswami, Dheeraj Kumar Sinha, Amitabh Chatterjee and Victor Koldyaev, "Use of RTA in Super-thin Body Structures to Replace Critical Implants," 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015), Bangalore.

  13. 13. S. Mondal and R. P. Paily, "An efficient on-chip energy processing circuit for micro-scale energy harvesting systems," VLSI Design and Test (VDAT), 2015 19th International Symposium on, Ahmedabad, 2015, pp. 1-5. doi: 10.1109/ISVDAT.2015.7208108

  14. 14. S. Mondal and R. P. Paily, "A strategy to enhance the output voltage of a charge pump circuit suitable for energy harvesting," Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013 Annual International Conference on, Kanjirapally, 2013, pp. 1-5. doi: 10.1109/AICERA-ICMiCR.2013.6575933

  15. 15. R. Roushan, D. Modak, S. Mondal and R. P. Paily, "On chip high voltage single clock swing enhanced charge pump circuit in 0.18 µm technology," Power and Energy in NERIST (ICPEN), 2012 1st International Conference on, Nirjuli, 2012, pp. 1-5. doi: 10.1109/ICPEN.2012.6492341

  16. 16. Maddirala A. K, and R. A. Shaik, "Removal of EMG artifacts from single channel EEG signal using singular spectrum analysis," 2015 IEEE International Circuits and Systems Symposium (ICSyS), Langkawi, 2015, pp. 111-115. doi: 10.1109/CircuitsAndSystems.2015.7394075.

  17. 17. A. K. Maddirala and R. A. Shaik, "Separation of artifacts from electroencephalogram signal using sequential singular spectrum analysis," Signal Processing And Communication Engineering Systems (SPACES), 2015 International Conference on, Guntur, 2015, pp. 384-388, doi: 10.1109/SPACES.2015.7058290

  18. 18. Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar, "Parallel Two Step Random Walk Algorithm to Analyze VLSI Power Grid Networks," IEEE 19th International Conference on VLSI Design and Test (VDAT), Ahmedabad, 2015.

  19. 19. Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Sachin B. Patkar and Gaurav Trivedi, "Power grid analysis on parallel computing platforms," IEEE 25th International Conference on Radioelektronika, CZ, 2015.

  20. 20. Deepak Joshi, Satyabrata Dash, Ujjawal Agarwal, Ratnajit Bhattacharjee and Gaurav Trivedi, "Analog Circuit Optimization Based on Hybrid Particle Swarm Optimization," IEEE International Conference on Computational Science and Computational Intelligence, Las Vegas, 2015.

  21. 21. Deepak Joshi, Satyabrata Dash, Ratnajit Bhattacharjee, Gaurav Trivedi, "A method of analog circuit optimization using adjoint sensitivity analysis," IEEE 25th International Conference on Radioelektronika, CZ, 2015. (Best Paper Award)

  22. 22. R. Shrestha and R. Paily, "Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique," Electronic System Design (ISED), 2014 Fifth International Symposium on, Surathkal, 2014, pp. 171-175. doi: 10.1109/ISED.2014.42

  23. 23. K. V. Kumar, R. Shrestha and R. Paily, "Design and implementation of multi-rate LDPC decoder for IEEE 802.16e wireless standard," Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on, Coimbatore, 2014, pp. 1-5. doi: 10.1109/ICGCCEE.2014.6922226

  24. 24. V. M. M., R. Paily and A. Mahanta, "Gain, NF and IIP3 Budgeting of LTE Receiver Front End," 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, Pune, 2013, pp. 191-196. doi: 10.1109/VLSID.2013.187

  25. 25. K. Singh and S. R. Ahamed, "Modified small-cross diamond search motion estimation algorithm for H.264/AVC," 2013 Annual IEEE India Conference (INDICON), Mumbai, 2013, pp. 1-5. doi: 10.1109/INDCON.2013.6726117

  26. 26. G. Saxena and R. Paily, "Transient Analysis of Bridge Microhotplate," IEEE International Conference on Advanced Electronic Systems 2013 (ICAES-2013), September 2013.

  27. 27. G. Saxena and R. Paily, "Effect of Membrane to Heater Ratio on the Performance of Square Micro-hotplate," IEEE International conference on microelectronics, communication and renewable energy (ICMICR), June 2013.

  28. 28. Prakash, M.S.; Shaik, R.A., "Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.60, no.11, pp.781,785, Nov. 2013 doi: 10.1109/TCSII.2013.2281747

  29. 29. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar and Roy Paily, "An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network", Lecture Notes in Computer Science, Springer Berlin / Heidelberg, Vol. 7373, pp 30-39, 2013.

  30. 30. R. Shrestha and R. Paily, "Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding," 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, Pune, 2013, pp. 86-91. doi: 10.1109/VLSID.2013.168

  31. 31. R. Shrestha and R. Paily, "System level hardware testing of a high speed MAP decoder implemented on FPGA," Signal Processing, Computing and Control (ISPCC), 2013 IEEE International Conference on, Solan, 2013, pp. 1-6. doi: 10.1109/ISPCC.2013.6663445

  32. 32. R. Shrestha and R. Paily, "A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder," Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on, Mysore, 2013, pp. 903-907. doi: 10.1109/ICACCI.2013.6637296

  33. 33. R. Shrestha and R. Paily, "Design of data width requirement for fixed-point turbo decoders based on modified MAP algorithm," 2012 International Conference on Signal Processing and Communications (SPCOM), Bangalore, 2012, pp. 1-5. doi: 10.1109/SPCOM.2012.6289997

  34. 34. G. Saxena and R. Paily, "Simulation Study of Power Loss Components in a Microheater," IEEE International Conference on Power and Energy in NERIST (ICPEN), December 2012.

  35. 35. G. Saxena and R. Paily, "Design of Microhotplate with Uniform Thermal Profile for Gas Sensing Ap-plication," ISSS National Conference on MEMS, Smart Materials, Structures and Systems, September 2012.

  36. 36. Suyog Jagtap and Roy Paily, "Fabrication Aspects of MEMS-based Energy Harvesting Device", Sixth International Conference on Smart Materials Structures and Systems (ISSS 2012), IISc, Bangalore, January 4 - 7, 2012

  37. 37. N. Ramakrishnan, Ashish Kumar Namdeo, Harshal B. Nemade, and Roy Paily Palathinkal, "A Finite Element Method Simulation of SAW delay Line Sensor using Periodic Boundary Conditions", in proc. International Conference on Advanced Nanomaterials and Nanotechnology, IIT Guwahati December 2011

  38. 38. Sudheer Kurakula, A. S. D. P. Sudhansh, Roy Paily and S. Dandapat, "Design of QRS Detection and Heart Rate Estimation System on FPGA" Book Chapter, Communications in Computer and Information Science, 1, Volume 193, Advances in Computing and Communications, Part 1, Pages 165-174

  39. 39. A. S. D. P. Sudhansh, Sudheer Kurakula, Roy Paily and S. Dandapat, "Implementation of Wavelet Transform based ECG Monitoring System for the Detection of QRS, P and T Waves", The International Conference on Data Engineering and Communication Systems (ICDECS 2011), RNSIT, Bangalore, December 30-31

  40. 40. V.S. Raju Mandapati, Nishanth P.V. and Roy Paily, "Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology", International Conference on VLSI, Communication and Instrumentation (ICVCI-11), Kottayam, Kerala, 7-9 April 2011 (Best paper award)

  41. 41. Suyog Jagtap and Roy Paily, "Geometry optimization of a MEMS-based energy harvesting device" IEEE Students' Technology Symposium 2011, IIT Kharagpur, 14-16 January 2011

  42. 42. K. C. Narasimhamurthy and Roy Paily, "Performance Comparison of Thin-Film Transistors Fabricated using Different Purity Semiconducting Nanotubes", appear in Proc. 24th Int. Conf. on VLSI Design, Jan. 2011, Chennai, India. pp. 208-213.

  43. 43. Rahul Shrestha and Roy Paily, "Hardware Implementation of Max-Log-MAP Algorithm based on MacLaurin Series for Turbo Decoder", International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011

  44. 44. Sunil Joshi and Roy Paily, "Low Power Viterbi Decoder by Modified ACSU architecture and Clock Gating Method", International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011

  45. 45. S. Sowmya and Roy Paily, "FPGA Implementation of Image Enhancement Algorithms", International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011

  46. 46. K. C. Narasimhamurthy and Roy Paily, "Fabrication and characterization of Carbon Nanotube thin-film Field Effect Transistor using sorted SWCNTs", in Proc. Int. Conf. on Advanced Material and Science, Oct. 2010, Trivandrum, Kerala, India, pp. 52-57

  47. 47. Deepak Balemarthy and Roy Paily, "Process Variations and Noise Analysis on a Miller Capacitance Tuned 1.8/2.4-GHz Dual-band Low Noise Amplifier", Advances in Computing, Control, and Telecommunication Technologies ACT 2009, Trivandrum, Kerala, 28 and 29 Dec 2009.

  48. 48. Banraplang Jyrwa and Roy Paily, "An Area-Throughput Efficient FPGA implementation of Block Cipher AES algorithm", Advances in Computing, Control, and Telecommunication Technologies ACT 2009, Trivandrum, Kerala, 28 and 29 Dec 2009.

  49. 49. Amlan Nag and Roy P. Paily "Low Power Squaring and Square root Circuits Using Subthreshold MOS Transistors", International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009), Institute of Technology Banaras Hindu University, Varanasi, India, Dec. 22-24, 2009.

  50. 50. B. Shankkar, Tarun Kumar and Roy Paily, "Low Power Biometric Capacitive CMOS Fingerprint Sensor System" 17th International Conference on Advanced Computing and Communications Conference (ADCOM) in Bangalore ADCOM 2009, Bangalore, 14 - 18 December 2009

  51. 51. Ashish Kumar Namdeo1, N. Ramakrishnan, Harshal B. Nemade and Roy Paily, "FEM Study on Contactless Excitation of Acoustic Waves in SAW Devices" COMSOL Conference, Bangalore, India, 13-14 Nov. 2009

  52. 52. Sanyasi Rao Rupiti, Diptaman Hazarika, Naveen Suda and Roy Paily, "A Low Power Inductive-Coupled Transceiver for Inter-Chip Communication" First Asian Himalayas International Conference on Internet AH-ICI2009, Kathmundu, Nepal, 3 - 5 November, 2009.

  53. 53. M. Kothamasu and Roy Paily, "Power Feeding and Digital Block design of Multi-standard Passive RFID Tag" First Asian Himalayas International Conference on Internet AH-ICI2009 Kathmundu, Nepal, 3 - 5 Nov. 2009.

  54. 54. K. C. Narasimhamurthy and Roy Paily, "Impact of Bias Voltage on Inductance of Carbon Nanotube Interconnects", 22nd International Conference on VLSI Design and the 8th International Conference on Embedded Systems, New Delhi, January 5th - 7th, 2009

  55. 55. Mustafijur Rahman and Roy Paily, "Building Blocks of an Implantable Microfluidic Chip to Control Blood Glucose Level by Insulin Delivery", International Conference on MEMS 2009 (ICMEMS 2009) IIT Madras, January 3-5, 2009

  56. 56. Parul Chopra, Neeraj Kumar and Roy Paily, "Ultra Wideband AGC and VGA designs for Software Radio Applications", IEEE Region 10 Conference, TENCON 2008, November 18-21, 2008, Hyderabad, India.

  57. 57. Sandeep Reddy Munnangi, Roy Paily, Rakesh Singh k, Genemala H and Manikumar K, "CMOS Capacitive Pressure Sensor Design and Integration with RFID Tag for Biomedical Applications", IEEE Region 10 Conference, TENCON 2008, November 18-21, Hyderabad, India

  58. 58. N. Ramakrishnan, Harshal B. Nemade, and Roy Paily Palathinkal, "Simplified finite element simulation of a SAW hydrogen sensor using COMSOL Multiphysics", COMSOL Multiphysics Conference, Germany, Nov.2008.

  59. 59. N. Ramakrishnan, Harshal B. Nemade and Roy Paily Palathinkal, "Finite element method study of SAW sensor for mass sensitivity" ICDF, Coimbatore, India, Aug. 2008.

  60. 60. Benny Thomas and Roy Paily, "Slew Rate Improvement Technique for High Frequency and Large Amplitude Signals", 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India

  61. 61. Neeraj Kumar, Parul Chopra and Roy Paily, "Ultra Wideband Variable Gain Amplifier Design for Software Defined Radio Applications", 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India

  62. 62. Sandeep Reddy Munnangi, Roy Paily, Rakesh Singh Kshetrimaym, Genemala Haobijam and Manikumar Kothamasu, "Sensor Integration in an RFID Tag for Monitoring Biomedical Signals", 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India

  63. 63. Rohan Kesireddy, Jyothi Bhaskarr Amarnadh, Genemala Haobijam and Roy Paily, "A Pulse Width Modulated DC-DC Buck Converter Using on-chip Inductor", 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India

  64. 64. Deepak Balemarthy and Roy Paily, "A 1.8/2.4-GHz Dualband CMOS Low Noise Amplifier Using Miller Capacitance Tuning, International Symposium on Low Power Electronics and Design 2008", August 11-13, 2008, Banglaore, India.

  65. 65. Niket Agrawal and Roy Paily, "An Improved ROM architecture for Bubble Error Suppression in High Speed Flash ADCs", Annual IEEE Student Paper Conference (AISPC'08), February 15th, 2008 at Aalborg University, Denmark.

  66. 66. P. Chopra, A. Kapoor, and R. Paily, "Acquisition, Storage and Analysis of Real Signals using FPGA, pp140-144, Proceedings of Workshop on Image and Signal Processing", WISP-2007, December 28-29, 2007, IIT Guwahati

  67. 67. Niket Agrawal and Roy Paily, "A Design Overview of Low Error Rate 800 MHz 6-bit CMOS Flash ADCs, pp 134-139, Proceedings of Workshop on Image and Signal Processing", WISP-2007, December 28-29, 2007, IIT Guwahati, India

  68. 68. Genemala Haobijam, Deepak Balemarthy and Roy Paily, "A 2.4 GHz CMOS Differential LNA with Multilevel Pyramidically Wound Symmetric Inductor in 0.18 µm Technology", pp 128-133, Proceedings of Workshop on Image and Signal Processing, WISP-2007, December 28-29, 2007, IIT Guwahati, India.

  69. 69. Genemala Haobijam, Manikumar and Roy Paily, "RFID Circuit Design with Optimized CMOS Inductor", 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.

  70. 70. Sathyaki and Roy Paily, "Leakage Reduction by Modified Stacking and Optimum Iso Input Loading in CMOS Devices", 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.

  71. 71. Prashanth Reddy Gade, Roy P Paily and Yajun Ha, "A Novel Branch Target Instruction Prefetching Technique for Improved Performance", 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.

  72. 72. Manikumar, Genemala Haobijam and Roy Paily, "Wireless Power Transmission in an RFID Tag for Monitoring Biomedical Signals", 10th International Symposium on Wireless Personal Multimedia Communication (WPMC 2007), December 03 - 06, 2007, Jaipur, India.

  73. 73. Genemala Haobijam and Roy Paily, "Quality Factor Enhancement of CMOS Inductor with Pyramidal Winding of Metal Turns", 14th International Workshop on The Physics of Semiconductor Devices, December 16-20, 2007, Mumbai, India.

  74. 74. Genemala Haobijam and Roy Paily, "A 2.4 GHz CMOS VCO with Multilevel Pyramidically Wound Symmetric Inductor in 0.35 µm CMOS Technology", INDICON 2007, Sept 2007.

  75. 75. Genemala Haobijam and Roy Paily, "Multilevel Symmetric Spiral Inductor with Reduced Area and Higher Self Resonating Frequency", Trends in VLSI and Embedded System, Indian Microelectronics Society (IMS) Conference, August 17-18, 2007, Chandigarh, India.

  76. 76. Krishna Chaitanya and Roy Paily, "Modified Data Encoding Circuit for Asynchronous FIFO Design", IIT Guwahati; 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.

  77. 77. Vikas Badam, Roy Paily and Yajun Ha, "Floating Gate Interferences on Vth Distribution In Eight Level High Density Flash Memory", 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.

  78. 78. Genemala Haobijam and Roy Paily, "Multilevel Pyramidically Wound Symmetric Spiral Inductor", 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.

  79. 79. N. Rama Krishnan, H. B. Nemade, and R. P. Paily, "Simulation of one port SAW resonator using COMSOL Multiphysics", COMSOL Multiphysics user Conference, Nov. 17, 2006, Bangalore, India (first prize for the best paper presented in the conference).

  80. 80. N. Rama Krishnan, H. B. Nemade, and R. P. Paily, "Modeling and analysis of SAW based liquid sensors", Eighth International Conference on Nanostructured Materials, Indian Institute of Science, Bangalore, August 20-25, 2006.

  81. 81. Genemala Haobijam and Roy Paily, Systematic Analysis, "Design and Optimization of On Chip Spiral Inductor for Silicon Based RFIC's", IEEE INDICON, Delhi, September, 15-17, 2006.

  82. 82. D. Vijaya Bhargava and Roy P. Paily, "Design & Study of an Electrostatic Torsion Micro Actuator for Beam Steering in Horizontal Plane", VLSI Design And Test Symposium 2006 - August 9-12, 2006 - Goa, India.

  83. 83. Genemala Haobijam and Roy Paily, "Design and Optimization of On-chip Spiral Inductor for Silicon Based RF IC'S", VLSI Design And Test Symposium 2006 - August 9-12, 2006 - Goa, India.

  84. 84. N. Rama Krishnan, R. P. Paily and H. B. Nemade. "Design of SAW based biosensor for heavy metal ion detection", The International Symposium on Nano-Bio Interface (Kolkata), March 1-3, 2006.

  85. 85. Amitava DasGupta, Roy Paily and Nandita DasGupta, "Improvement in Breakdown field strength of thin thermally grown SiO2 by selective anodic oxidation. (Invited Paper)", Proceedings of International Conference on Communications, Devices & Intelligent Systems (CODIS2004), p. 400 - 403, Kolkata, January 2004.

  86. 86. Paily, R., A. DasGupta, N. DasGupta, P. Mishra and L. M. Kukreja, "Effect of Low Temperature Buffer Layers during Pulsed Laser Deposition of TiO2 on MTOS (Metal-TiO2-SiO2-Si) Capacitor Characteristics". Proceedings of 12th International Workshop on Physics of Semiconductor Devices, IIT Madras, December, 2003, 480-482.

  87. 87. Marathe, V. G., R. Paily, N. DasGupta and A. DasGupta, "Study of Effect of Selective Anodic Oxidation on Electrical Characteristics of MOS Capacitors with Ultrathin Gate Oxide Grown at Different Temperatures". Proceedings of 12th International Workshop on Physics of Semiconductor Devices, IIT Madras, December, 2003, 483-485.

  88. 88. DasGupta, N., R. Paily, A. DasGupta, T. Ganguli, P. Misra, P. Bhattacharya and L. M. Kukreja, "Pulsed Laser Deposition of TiO2 to realize MTOS (Metal-TiO2 -SiO2 -Si) Capacitor". DAE-BRNS Topical Meeting on Pulsed Laser Deposition of Thin Films (PLD - 2001), CAT Indore, November, 2001.

  89. 89. Paily, R., A. DasGupta and N. DasGupta. "Improvement in Breakdown Field Strength of Thin Thermally Grown SiO2 by Selective Anodic Oxidation". Proceedings of 11th International Workshop on Physics of Semiconductor Devices, New Delhi, December, 2001, 229-232 (Best poster award)

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