Roy Paily

Dr. Roy P. Paily

Head, Centre for Nanotechnology

Professor, Department of Electronics and Electrical Engineering

IIT Guwahati

Books

  1. "Design and Analysis of Spiral Inductors" Genemala Haobijam (Author) and Roy Paily Palathinkal (Author), Springer, October 2013.

International Journals

  1. Brajesh Rawat and Roy Paily, “Analysis of Graphene Tunnel Field-Effect Transistors for Analog/RF Applications”, IEEE Transactions on Electron Devices, (Accepted) .
  2. Nagesh Ch and Roy Paily,"Design of an Osmotic Pressure Sensor for Sensing Osmotically Active Substance", Journal of Micromechanics and Microengineering, IOP Publishing, Volume 25 Number 4, 045019 2015.
  3. Ratul Kr Baruah and Roy Paily, "The Effect of High-k Gate Dielectrics on Device and Circuit Performances of a Junctionless Transistor" Journal of Computational Electronics, Springer, (accepted), 2015.
  4. Sachin Kumawat, Rahul Shrestha, Nikunj Daga and Roy Paily, “High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule", IEEE Transactions on Circuits and Systems I, Vol. 62, No. 5, MAY 2015.
  5. Nagesh Ch and Roy Paily,"Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application", Micromachines 5, no. 3 (2014): 722-737
  6. Suda, Naveen, P. V. Nishanth, Debajit Basak, Durshee Sharma and Roy Paily "A 0.5-V low power analog front-end for heart-rate detector." Analog Integrated Circuits and Signal Processing, Springer, Vol. 81 Issue 2, Pages 417-430, November 2014.
  7. Rahul Shrestha and Roy Paily, “Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder", Journal of Signal Processing Systems, Springer (2014).
  8. Rahul Shrestha and Roy Paily, “High-Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards", IEEE Transactions on Circuits and Systems I, Vol. 61, Issue: 9, pp 2699 - 2710, 2014.
  9. Ratul Kumar Baruah and Roy Paily, “A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance”, IEEE Transactions on Electron Devices, Vol. 61, NO. 1, pp. 123-128, January 2014.
  10. Sunil Joshi and Roy Paily,"Distributed Arithmetic based Split-Radix FFT", Springer, Journal of Signal Processing Systems: Volume 75, Issue 1 (2014), Page 85-92.
  11. G. Saxena and R. Paily “Choice of insulation materials and its effect on the performance of square microhotplate,” Microsystem Technologies, Springer, 1-7, (2013).
  12. G. Saxena and R. Paily “Analytical modeling of square microhotplate for gas sensing application,” Sensors Journal, IEEE, Vol. 13, no. 12, pp. 4851–4859, 2013.
  13. Rahul Shrestha and Roy Paily, “Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo- broadcasting-satellite-services-tohandhelds standard”, IET Communications, The Institution of Engineering and Technology, Volume 7, Issue 12, pages. 1211 – 1220, 2013.
  14. Ratul Kumar Baruah and Roy Paily, “A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance”, Lecture Notes in Computer Science, Springer Berlin / Heidelberg, Vol. 7373, pp 30-39, 2013.
  15. Ratul Kumar Baruah and Roy Paily, “Double-gate junctionless transistor for Analog Applications", Journal of Nanoscience and Nanotechnology, Vol. 13, no. 3, 1802-1807, 2013.
  16. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar and Roy Paily, “An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network”, Lecture Notes in Computer Science, Springer Berlin / Heidelberg, Vol. 7373, pp 30-39, 2013.
  17. R. Gnana Praveen and Roy Paily,"Blind Navigation Assistance for Visually Impaired Based on Local Depth Hypothesis from a Single Image", International Conference on Design and manufacturing, IConDM 2013, Procedia Engineering, Elsevier, Volume 64, pages 351 – 360, 2013
  18. Nagesh Ch and Roy Paily,"High Sensitivity Microbridge for Molecular Sensing Applications", International Conference on Design and manufacturing, IConDM 2013, Procedia Engineering, Elsevier, Volume 64, Pages 234–243, 2013
  19. Vimal K Mohandas and Roy Paily, "Stereo Disparity Estimation Algorithm for Blind Assisting System" CSI Transactions on ICT, Springer, Volume 1, Issue 1, Page 3-8, 2013.
  20. Ratul Kr Baruah and Roy Paily, "Impact of High-k Spacer on Device Performance of a Junctionless Transistor" Journal of Computational Electronics, Springer, Volume 12, Issue 1, pp 14-19, 2013
  21. K. C. Narasimhamurthy and Roy Paily, "Wafer Scale Thin-Film Transistors using Different Semiconducting Purity Nanotubes, Dielectric Materials and Gate Control" Solid State Electronics, Elsevier, Volume 79, Pages 37–44, January 2013.
  22. Rahul Shrestha and Roy Paily, “Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding”, Lecture Notes in Computer Science, LNCS 7373, Springer Berlin / Heidelberg, H. Rahaman et al. (Eds.): VDAT 2012, pp. 30–39, 2012.
  23. N. Ramakrishnan, Ashish Kumar Namdeo, Harshal B. Nemade and Roy Paily Palathinkal, “Simplified model for FEM simulation of SAW delay line sensor,” Elsevier Procedia Engineering, Vol. 41, pp. 1022-1027, 2012
  24. Abdul Raouf Khalid and Roy Paily, “FPGA Implementation of High Speed and Low Power Architectures for Image Segmentation Using Sobel Operators”, Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, Vol. 21, No. 7, 1250050 - 14 pages, 2012.
  25. Ramakrishnan, N., Nemade, H.B. and Palathinkal Roy Paily, “Resonant Frequency Characteristics of a SAW Device Attached to Resonating Micropillars”, Multidisciplinary Digital Publishing Institute (MDPI) Sensors, 12(4), pp 3789-3797, 2012.
  26. N. Ramakrishnan, Harshal B. Nemade, Roy Paily Palathinkal, “Fabrication of High Aspect Ratio SU-8 Microstructures on Piezoelectric Transducers”, Journal of Applied Mechanics and Materials, Trans Tech Publications Ltd. Switzerland, Volumes 110 – 116, Pages 3127-3131, 2011.
  27. N. Ramakrishnan, Harshal B. Nemade, Roy Paily Palathinkal, “Investigation on Resonance Effects of Closely Resonating Nano-Pillars Attached to SAW Resonator”, Journal of Applied Mechanics and Materials, Trans Tech Publications Ltd. Switzerland, Volumes 403 – 408, Pages 1183-1187, 2011
  28. Ramakrishnan, N., Nemade, H.B. and Palathinkal R.P “Mass Loading in Coupled Resonators Consisting of SU-8 Micropillars Fabricated Over SAW Devices” IEEE Journal Sensors, Vol.11, Issue 2, 430 – 431, 2011 .
  29. K. C. Narasimhamurthy and Roy Paily, High Performance Local Back Gate Thin-Film Field-Effect Transistors using Sorted Carbon Nanotubes on Amino-Silane Treated Hafnium-Oxide Surface," Semiconductor Science and Technology., 26 (2011).
  30. K. C. Narasimhamurthy and Roy Paily, Performance Comparison of Single Gate and Dual Gate Carbon Nanotube Thin-Film Field-Effect Transistors," IEEE Transactions on Electron Devices, Vol. 58 , Issue 7, 1922 – 1927, 2011.
  31. K. C. Narasimhamurthy and Roy Paily, “Fabrication and Characterization of High Performance and High Current Back Gate Thin-Film Field-Effect Transistors using Sorted Single Walled Carbon Nanotubes”, IET Circuits, Devices & Systems, Vol. 5, Iss. 5, pp 365–370, 2011.
  32. K. C. Narasimhamurthy and Roy Paily, Fabrication and Performance Comparison of Interdigitated Thin-Film Field-Effect Transistors using Different Purity Semiconducting Carbon Nanotubes," Advanced Materials Research, Vol. 181-182, pp. 343-348, Jan. 2011.
  33. N. Ramakrishnan, T. Vamsi, A. Khan, Harshal B. Nemade, and Roy Paily Palathinkal, “Humidity sensor using NIPAAm Nanogel as sensing medium in SAW devices,” International Journal of Nanoscience, Vol. 10, pp. 259-262, 2011.
  34. V.S. Raju Mandapati, Nishanth P.V. and Roy Paily, “Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology”, International Journal of Computer Science Issues, Volume 1, Issue 1, November 2011 (Best paper award International Conference on VLSI, Communication and Instrumentation ICVCI-11, Kottayam, Kerala, 7-9 April 2011).
  35. A. Ramesh Babu and Roy Paily, “Power-Delay Reduction in FPGA Implementations Using Bypassing Technique” International Journal of Recent Trends in Engineering, Vol. 4, No. 4, Nov 2010.
  36. N. Ramakrishnan, Roy Paily Palathinkal, and Harshal B. Nemade, “Mass loading effects of high aspect ratio structures grown over SAW resonators,” Sensor Letters, 2010, vol. 8, No. 2, pp. 253-257, Copyright © 2010 American Scientific Publishers.
  37. N. Ramakrishnan, Harshal B. Nemade, and Roy Paily Palathinkal “Finite element simulation of a surface acoustic wave hydrogen sensor with palladium nano-pillars as sensing medium,” Sensor Letters, 2010, vol. 8, No. 6, pp. 824-828, , Copyright © 2010 American Scientific Publishers.
  38. Genemala Haobijam and Roy Paily, “Design of Multilevel Pyramidically Wound Symmetric Inductor for CMOS RFICs,” Analog Integrated Circuits and Signal Processing, Springer, September 2009.
  39. Niket Agrawal and Roy Paily, A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS, Analog Integrated Circuits and Signal Processing, Springer, September 2009.
  40. Genemala Haobijam and Roy Paily, Performance Study of Fixed Value Inductors and their Optimization using Electromagnetic Simulator, Microwave and Optical Technology Letters, Wiley Interscience, Volume 50, Issue 5, pp 1205 – 1210, May 2008.
  41. Genemala Haobijam and Roy Paily, Efficient Optimization of Integrated Spiral Inductor with Bounding of Layout Design Parameters, Analog Integrated Circuits and Signal Processing, Springer, Vol 51, no.3, pp 131-140, June 2007.
  42. Marathe, V. G., R. Paily, N. DasGupta and A. DasGupta, A model to study the effect of Selective Anodic Oxidation on ultrathin gate oxides, IEEE Transactions on Electron Devices, Volume 52, Issue 1, pp 118 – 121, 2005.
  43. Paily, R., A. DasGupta N. DasGupta, T. Ganguli and L. M. Kukreja. Effect of Oxygen Pressure and Laser Fluence during Pulsed Laser Deposition of TiO2 on MTOS (Metal-TiO2-SiO2-Si) Capacitor Characteristics. Thin Solid Films, 462-463, 57-62, 2004.
  44. Singh, R., Paily, R., A. DasGupta, N. DasGupta, P. Misra and L. M. Kukreja Optimized Dual Temperature Pulsed Laser Deposition of TiO2 to Realize MTOS (Metal-TiO2 -SiO2 -Si) Capacitors with Ultrathin Gate Dielectric. Semiconductor Science and Technology, 20, 38-43, 2004.
  45. Singh, R.; Paily, R. DasGupta, A. DasGupta, N. Misra, P. and L.M. Kukreja Laser induced oxidation for growth of ultrathin gate oxide. Electronics Letters, 40, 1606-1607, 2004.
  46. Paily, R., A. DasGupta, N. DasGupta, P. Bhattacharya, P. Misra, T. Ganguli, L. M. Kukreja, A.K. Balamurugan, S. Rajagopalan and A.K. Tyagi, Pulsed Laser Deposition of TiO2 for MOS Gate Dielectric. Applied Surface Science, 187, 297–304. 2002 .
  47. Paily, R., A. DasGupta and N. DasGupta, Improvement in Electrical Characteristics of Ultrathin Thermally Grown SiO2 by Selective Anodic Oxidation, IEEE Electron Device Letters, 23, 707-709, 2002.

National Journals

  1. Deepak Balemarthy and Roy Paily, 1.6/1.8/2.1/2.4-GHz Multiband CMOS Low Noise Amplifier, Special Issue of IETE Journal of Research on Microwave Circuits and Systems, IETE Journal of Research, Vol. 54, No 1, Jan-Feb 2008.
  2. Narasimhamurthy, K.C., Roy Paily, “Fabrication of carbon nanotube field effect transistor”, IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India, 28 (1), pp. 57-69, 2011.
  3. Durshee Sharma and Roy Paily, “Multi-standard Σ - Δ Modulator for GSM/WCDMA Applications”, IETE Journal of Research, Vol. 58, No. 4, pp 292-297.

International/National Conferences

  1. Paily, R., A. DasGupta and N. DasGupta. Improvement in Breakdown Field Strength of Thin Thermally Grown SiO2 by Selective Anodic Oxidation. Proceedings of 11th International Workshop on Physics of Semiconductor Devices, New Delhi, December, 2001, 229-232 (Best poster award).
  2. DasGupta, N., R. Paily, A. DasGupta, T. Ganguli, P. Misra, P. Bhattacharya and L. M. Kukreja. Pulsed Laser Deposition of TiO2 to realize MTOS (Metal-TiO2 -SiO2 -Si) Capacitor. DAE–BRNS Topical Meeting on Pulsed Laser Deposition of Thin Films (PLD – 2001), CAT Indore, November, 2001.
  3. Marathe, V. G., R. Paily, N. DasGupta and A. DasGupta. Study of Effect of Selective Anodic Oxidation on Electrical Characteristics of MOS Capacitors with Ultrathin Gate Oxide Grown at Different Temperatures. Proceedings of 12th International Workshop on Physics of Semiconductor Devices, IIT Madras, December, 2003, 483-485.
  4. Paily, R., A. DasGupta, N. DasGupta, P. Mishra and L. M. Kukreja. Effect of Low Temperature Buffer Layers during Pulsed Laser Deposition of TiO2 on MTOS (Metal-TiO2-SiO2-Si) Capacitor Characteristics. Proceedings of 12th International Workshop on Physics of Semiconductor Devices, IIT Madras, December, 2003, 480-482.
  5. Amitava DasGupta, Roy Paily and Nandita DasGupta. Improvement in Breakdown field strength of thin thermally grown SiO2 by selective anodic oxidation. (Invited Paper), Proceedings of International Conference on Communications, Devices & Intelligent Systems (CODIS2004), p. 400 - 403, Kolkata, January 2004.
  6. N. Rama Krishnan, R. P. Paily and H. B. Nemade. Design of SAW based biosensor for heavy metal ion detection, the International Symposium on Nano-Bio Interface (Kolkata), March 1–3, 2006.
  7. Genemala Haobijam and Roy Paily, Design and Optimization of On-chip Spiral Inductor for Silicon Based RF IC'S, VLSI Design And Test Symposium 2006 – August 9-12, 2006 – Goa, India.
  8. D. Vijaya Bhargava and Roy P. Paily, Design & Study of an Electrostatic Torsion Micro Actuator for Beam Steering in Horizontal Plane, VLSI Design And Test Symposium 2006 – August 9-12, 2006 – Goa, India.
  9. Genemala Haobijam and Roy Paily, Systematic Analysis, Design and Optimization of On Chip Spiral Inductor for Silicon Based RFIC’s, IEEE INDICON, Delhi, September, 15-17, 2006.
  10. N. Rama Krishnan, H. B. Nemade, and R. P. Paily, “Modeling and analysis of SAW based liquid sensors,” Eighth International Conference on Nanostructured Materials, Indian Institute of Science, Bangalore, August 20–25, 2006.
  11. N. Rama Krishnan, H. B. Nemade, and R. P. Paily, “Simulation of one port SAW resonator using COMSOL Multiphysics,” COMSOL Multiphysics user Conference, Nov. 17, 2006, Bangalore, India (first prize for the best paper presented in the conference).
  12. Genemala Haobijam and Roy Paily, Multilevel Pyramidically Wound Symmetric Spiral Inductor, 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.
  13. Vikas Badam, Roy Paily and Yajun Ha, Floating Gate Interferences on Vth Distribution In Eight Level High Density Flash Memory, 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.
  14. Krishna Chaitanya and Roy Paily, Modified Data Encoding Circuit for Asynchronous FIFO Design, IIT Guwahati; 11th IEEE VLSI Design And Test Symposium, August 8-11, 2007, Kolkata, India.
  15. Genemala Haobijam and Roy Paily, Multilevel Symmetric Spiral Inductor with Reduced Area and Higher Self Resonating Frequency, Trends in VLSI and Embedded System, Indian Microelectronics Society (IMS) Conference, August 17-18, 2007, Chandigarh, India.
  16. Genemala Haobijam and Roy Paily, A 2.4 GHz CMOS VCO with Multilevel Pyramidically Wound Symmetric Inductor in 0.35 µm CMOS Technology, INDICON 2007, Sept 2007.
  17. Genemala Haobijam and Roy Paily, Quality Factor Enhancement of CMOS Inductor with Pyramidal Winding of Metal Turns, 14th International Workshop on The Physics of Semiconductor Devices, December 16-20, 2007, Mumbai, India.
  18. Manikumar, Genemala Haobijam and Roy Paily, Wireless Power Transmission in an RFID Tag for Monitoring Biomedical SignalsThe 10th International Symposium on Wireless Personal Multimedia Communication (WPMC 2007), December 03 - 06, 2007, Jaipur, India.
  19. Prashanth Reddy Gade, Roy P Paily and Yajun Ha, A Novel Branch Target Instruction Prefetching Technique for Improved Performance, 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.
  20. Sathyaki and Roy Paily, Leakage Reduction by Modified Stacking and Optimum Iso Input Loading in CMOS Devices, 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.
  21. Genemala Haobijam, Manikumar and Roy Paily, RFID Circuit Design with Optimized CMOS Inductor, 15th International Conference on Advanced Computing & Communication, 18 - 21 December, 2007, Guwahati, India.
  22. Genemala Haobijam, Deepak Balemarthy and Roy Paily, A 2.4 GHz CMOS Differential LNA with Multilevel Pyramidically Wound Symmetric Inductor in 0.18 µm Technology, pp 128-133, Proceedings of Workshop on Image and Signal Processing, WISP-2007, December 28-29, 2007, IIT Guwahati, India.
  23. Niket Agrawal and Roy Paily, A Design Overview of Low Error Rate 800 MHz 6-bit CMOS Flash ADCs, pp 134-139, Proceedings of Workshop on Image and Signal Processing, WISP-2007, December 28-29, 2007, IIT Guwahati, India.
  24. P. Chopra, A. Kapoor, and R. Paily, Acquisition, Storage and Analysis of Real Signals using FPGA, pp140-144, Proceedings of Workshop on Image and Signal Processing, WISP-2007, December 28-29, 2007, IIT Guwahati.
  25. Niket Agrawal and Roy Paily, An Improved ROM architecture for Bubble Error Suppression in High Speed Flash ADCs , Annual IEEE Student Paper Conference (AISPC'08), February 15th, 2008 at Aalborg University, Denmark.
  26. Deepak Balemarthy and Roy Paily, A 1.8/2.4-GHz Dualband CMOS Low Noise Amplifier Using Miller Capacitance Tuning, International Symposium on Low Power Electronics and Design 2008, August 11-13, 2008, Banglaore, India.
  27. Rohan Kesireddy, Jyothi Bhaskarr Amarnadh, Genemala Haobijam and Roy Paily, A Pulse Width Modulated DC-DC Buck Converter Using on-chip Inductor, 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India.
  28. Sandeep Reddy Munnangi, Roy Paily, Rakesh Singh Kshetrimaym, Genemala Haobijam and Manikumar Kothamasu, Sensor Integration in an RFID Tag for Monitoring Biomedical Signals, 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India.
  29. Neeraj Kumar, Parul Chopra and Roy Paily, Ultra Wideband Variable Gain Amplifier Design for Software Defined Radio Applications, 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India.
  30. Benny Thomas and Roy Paily, Slew Rate Improvement Technique for High Frequency and Large Amplitude Signals, 12th IEEE VLSI Design and Test Symposium, July 23-26, 2008, Bangalore, India.
  31. N. Ramakrishnan, Harshal B. Nemade and Roy Paily Palathinkal, “Finite element method study of SAW sensor for mass sensitivity” ICDF, Coimbatore, India, Aug. 2008.
  32. N. Ramakrishnan, Harshal B. Nemade, and Roy Paily Palathinkal, “Simplified finite element simulation of a SAW hydrogen sensor using COMSOL Multiphysics,” COMSOL Multiphysics user Conference (Germany), Nov. 2008.
  33. Sandeep Reddy Munnangi, Roy Paily, Rakesh Singh k, Genemala H and Manikumar K, CMOS Capacitive Pressure Sensor Design and Integration with RFID Tag for Biomedical Applications, IEEE Region 10 Conference, TENCON 2008, November 18-21, Hyderabad, India.
  34. Parul Chopra, Neeraj Kumar and Roy Paily, Ultra Wideband AGC and VGA designs for Software Radio Applications, IEEE Region 10 Conference, TENCON 2008, November 18-21, 2008, Hyderabad, India.
  35. Mustafijur Rahman and Roy Paily, Building Blocks of an Implantable Microfluidic Chip to Control Blood Glucose Level by Insulin Delivery, International Conference on MEMS 2009 (ICMEMS 2009) IIT Madras, January 3–5, 2009.
  36. K. C. Narasimhamurthy and Roy Paily, Impact of Bias Voltage on Inductance of Carbon Nanotube Interconnects, 22nd International Conference on VLSI Design and the 8th International Conference on Embedded Systems, New Delhi, January 5th - 7th, 2009
  37. M. Kothamasu and Roy Paily, “Power Feeding and Digital Block design of Multi-standard Passive RFID Tag” First Asian Himalayas International Conference on Internet AH-ICI2009 Kathmundu, Nepal, 3 - 5 November, 2009.
  38. Sanyasi Rao Rupiti, Diptaman Hazarika, Naveen Suda and Roy Paily, “A Low Power Inductive-Coupled Transceiver for Inter-Chip Communication” First Asian Himalayas International Conference on Internet AH-ICI2009, Kathmundu, Nepal, 3 - 5 November, 2009.
  39. Ashish Kumar Namdeo1, N. Ramakrishnan, Harshal B. Nemade and Roy Paily, “FEM Study on Contactless Excitation of Acoustic Waves in SAW Devices” COMSOL Conference, Bangalore, India, 13-14 November 2009.
  40. B. Shankkar, Tarun Kumar and Roy Paily, “Low Power Biometric Capacitive CMOS Fingerprint Sensor System” 17th International Conference on Advanced Computing and Communications Conference (ADCOM) in Bangalore ADCOM 2009, Bangalore, 14 – 18 December 2009.
  41. Amlan Nag and Roy P. Paily “Low Power Squaring and Square root Circuits Using Subthreshold MOS Transistors”, International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009), Institute of Technology Banaras Hindu University, Varanasi, India, December 22-24, 2009.
  42. Banraplang Jyrwa and Roy Paily, “An Area-Throughput Efficient FPGA implementation of Block Cipher AES algorithm”, Advances in Computing, Control, and Telecommunication Technologies ACT 2009, Trivandrum, Kerala, 28 and 29 Dec 2009.
  43. Deepak Balemarthy and Roy Paily, “Process Variations and Noise Analysis on a Miller Capacitance Tuned 1.8/2.4-GHz Dual-band Low Noise Amplifier”, Advances in Computing, Control, and Telecommunication Technologies ACT 2009, Trivandrum, Kerala, 28 and 29 Dec 2009.
  44. N. Ramakrishnan, Harshal B. Nemade, Roy Paily Palathinkal “Mass loading effect of high aspect ratio structures fabricated over SAW resonators” 3rd INUP workshop on Nanoelectronics, IISc Bangalore, India (Invited) 2010.
  45. K. C. Narasimhamurthy and Roy Paily, Fabrication and characterization of Carbon Nanotube thin-film Field Effect Transistor using sorted SWCNTs," in Proc. Int. Conf. on Advanced Material and Science, Oct. 2010, Trivandrum, Kerala, India, pp. 52-57.
  46. S. Sowmya and Roy Paily, “FPGA Implementation of Image Enhancement Algorithms” International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011.
  47. Sunil Joshi and Roy Paily, “Low Power Viterbi Decoder by Modified ACSU architecture and Clock Gating Method” International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011.
  48. Rahul Shrestha and Roy Paily, “Hardware Implementation of Max-Log-MAP Algorithm based on MacLaurin Series for Turbo Decoder” International Conference on Communications and Signal Processing (ICCSP), NIT Calicut, India, 10-12 Feb. 2011.
  49. K. C. Narasimhamurthy and Roy Paily, Performance Comparison of Thin-Film Transistors Fabricated using Different Purity Semiconducting Nanotubes," Proc. 24th International Conference on VLSI Design, Jan. 2011, Chennai, India. pp. 208-213.
  50. Suyog Jagtap and Roy Paily, “Geometry optimization of a MEMS-based energy harvesting device” IEEE Students' Technology Symposium 2011, IIT Kharagpur, 14-16 January 2011 .
  51. Sudheer Kurakula, A. S. D. P. Sudhansh, Roy Paily and S. Dandapat, “Design of QRS Detection and Heart Rate Estimation System on FPGA” Book Chapter, Communications in Computer and Information Science, 1, Volume 193, Advances in Computing and Communications, Part 1, Pages 165-174.
  52. A. S. D. P. Sudhansh, Sudheer Kurakula, Roy Paily and S. Dandapat, “Implementation of Wavelet Transform based ECG Monitoring System for the Detection of QRS, P and T Waves”, The International Conference on Data Engineering and Communication Systems (ICDECS 2011), RNSIT, Bangalore, December 30-31.
  53. N. Ramakrishnan, Ashish Kumar Namdeo, Harshal B. Nemade, and Roy Paily Palathinkal, “A Finite Element Method Simulation of SAW delay Line Sensor using Periodic Boundary Conditions,” in proc. International Conference on Advanced Nanomaterials and Nanotechnology, IIT Guwahati December 2011.
  54. Suyog Jagtap and Roy Paily, “Fabrication Aspects of MEMS-based Energy Harvesting Device”, Sixth International Conference on Smart Materials Structures and Systems (ISSS 2012), IISc, Bangalore, January 4 - 7, 2012.
  55. Amrita Brahmachari and Roy Paily, “Low Power 2.4 GHz RF Transmitter for Satellite Subsystem Using Cordic Based Frequency Translator”, Ninth International Conference on Wireless and Optical Communications Networks (WOCN2012) INDORE, 21-22 September, 2012.
  56. Rahul Shrestha and Roy Paily, “Design of data width requirement for fixed-point turbo decoders based on modified MAP algorithm”, International Conference on Signal Processing and Communications (SPCOM), 2012, Bangalore, India, July 2012.
  57. Gaurav Saxena and Roy Paily, “Design of Microhotplate with Uniform Thermal Profile for Gas Sensing Application”, fifth ISSS National Conference on MEMS, Smart Materials, Structures and Systems, Karpagam University, Coimbatore, September, 2012.
  58. Nagesh CH and Roy Paily, “FEM AND FVM Simulations of Osmotic Microactuator”, fifth ISSS National Conference on MEMS, Smart Materials, Structures and Systems, Karpagam University, Coimbatore, September, 2012.
  59. Srinivas Boina and Roy Paily, "Comparison of DAC Architectures of SAR ADCs" Fourth International Conference on Advances in Recent Technologies in Communication and Computing, ARTCom 2012, Bangalore India, Oct 19-20, 2012.
  60. Rahul Roushan, Dipyaman Modak, Saroj Mondal and Roy Paily, “On Chip High Voltage Single Clock Swing Enhanced Charge Pump Circuit in 0.18 μm Technology”, 1st International Conference on Power and Energy in NERIST, Arunachal Pradesh, India, December 28-29, 2012.
  61. Gaurav Saxena and Roy Paily, “Simulation Study of Power Loss Components in a Microheater”, 1st International Conference on Power and Energy in NERIST, Arunachal Pradesh, India, December 28-29, 2012.
  62. Ratul Kumar Baruah and Roy Paily Palathinkal, “Silicon vs. Germanium Bulk Planar Junctionless Transistor" 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM 2012), Berkeley, California, USA, pp 164-165, 4 – 6 June 2012.
  63. Rahul Shrestha and Roy Paily, “Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding”, 26th International Conference on VLSI Design, Jan. 2013, Pune, India.
  64. Vinay M M, Roy Paily and Anil Mahanta “Gain, NF and IIP3 Budgeting of LTE Receiver Front End”, 26th International Conference on VLSI Design, Jan. 2013, Pune, India.
  65. Ratul Kumar Baruah and Roy Paily “Estimation of Process-Induced Variations In Double-Gate Junctionless Transistor”, 5th International Conference on Computers and Devices for Communication (CODEC 2012), Kolkata, India.
  66. Ratul Kumar Baruah and Roy Paily "Analog Performance of Bulk Planar Junctionless Transistor", IEEE ICCCNT 2012, Tamilnadu, India, 2012.
  67. Ratul Kumar Baruah and Roy Paily "High-Temperature Effects on Device Performance of a Junctionless Transistor”, IEEE ICEE 2012, 15-17 Dec., IIT Bombay, India.
  68. Srinivas Boina and Roy Paily “A 23.1 µ W 8 Bit 1.1MS/s SAR ADC with Counter Based Control Logic”, 2012 Annual IEEE India Conference (INDICON 2012), Kochi, India.
  69. Gaurav Saxena and Roy Paily “Effect of Membrane to Heater Ratio on the Performance of Square Microhotplate”, IEEE International conference on Microelectronics, Communication and Renewable Energy (ICMiCR 13), Kochi, India, June 4-6, 2013.
  70. Saroj Mondal and Roy Paily “A Strategy to Enhance the Output Voltage of a Charge Pump Circuit Suitable for Energy Harvesting”, IEEE International conference on Microelectronics, Communication and Renewable Energy (ICMiCR 13), Kochi, India, June 4-6, 2013.
  71. Rahul Shrestha and Roy Paily, “A Novel State Metric Normalization Technique and an Implementation of High Throughput MAP Decoder”, International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013),SJCE, Mysore, Karnataka, India, August 22-25, 2013.
  72. Ratul Kumar Baruah and Roy Paily “Double-Gate Junctionless Transistor for Low Power Digital Applications”, International Conference on Emerging Trends and Applications in Computer Science, St. Anthony’s College Shillong, 13-14 September, 2013 Meghalaya, India.
  73. Gaurav Saxena and Roy Paily “Transient Analysis of Bridge Microhotplate", International Conference on Advanced Electronic Systems (ICAES-2013), CSIR-CEERI, Pilani, India, September 21-23, 2013.
  74. Debajit Basak, Nishanth PV and Roy Paily “A Low Noise Preamplifier and Filter For Heart-rate Detector", International Conference on Advanced Electronic Systems (ICAES-2013), CSIR-CEERI, Pilani, India, September 21-23, 2013.
  75. Shrestha, Rahul and Roy Paily "System level hardware testing of a high speed MAP decoder implemented on FPGA." In Signal Processing, Computing and Control (ISPCC), 2013 IEEE International Conference on, pp. 1-6. IEEE, 2013.
  76. Vijaya Kumar K, Rahul Shrestha and Roy Paily “Design and Implementation of Multi-Rate LDPC Decoder for IEEE 802.16e Wireless Standard" IEEE International Conference on Green Computing, Communication and Electrical Engineering-ICGCCEE’14, Coimbatore, March 6-8, 2014.
  77. Mridul Krishna and Roy Paily “Efficient Rectifier Design for Wearable Healthcare Applications" IEEE International Conference on Green Computing, Communication and Electrical Engineering-ICGCCEE’14, Coimbatore, March 6-8, 2014.
  78. Joseph, F.; Francis, K.; Hore, A.; Roy, S.; Josephine, S. and Paily, R.P., "An efficient hardware architecture for stereo disparity estimation", 18th International Symposium on VLSI Design and Test Symposium, 2014, Coimbatore, July 16 -18, India.
  79. Namami Goswami, Ujjwol Barman, Roy Paily, Biplab Bose and Siddhartha Sankar Ghosh “A Highly Sensitive Lithium Niobate Based Microcantilever for Biosensing Applications”, International Conference on Emerging Trends in Electrical Engineering, ICETREE, Kollam, Kerala, 4-6 August, 2014.
  80. Ratul Kumar Baruah and Roy Paily “Impact of Fringing Fields in a p-Channel Junctionless Transistor”, International Conference on Emerging Electronics (ICEE), Indian Institute of Science Bangalore, 4-6 December, 2014.
  81. Brajesh Rawat and Roy Paily “PerformanceComparison between Graphene based Conventional MOSFET and TFET for Analog Circuits" Conference on TransportProperties in Low Dimensional Systems: Experiment and Simulation(TransLES-2014), IASST, Guwahati, 11-13, December 2014.
  82. Rahul Shrestha and Roy Paily, “Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel un-Grouped Sliding-Window Technique,” IEEE 5th International Symposium on Electronics System Design (ISED), Mangalore, December 15 - 17, 2014.