Roy Paily

Dr. Roy P. Paily

Head, Centre for Nanotechnology

Professor, Department of Electronics and Electrical Engineering

IIT Guwahati

Consultancy/Research Projects:

  1. "Centre for Excellence in Research and Development of Nanoelectronic Theranostic Devices" at IIT Guwahati, Department of Electronics & Information Technology, Ministry of Communications & Information Technology, Government of India (one of the Investigators).
  2. "Design and Implementation of a Blind Assistance System using FPGAs and Sensors" at IIT Guwahati, Department of Information Technology, India (Investigator).
  3. "Design of Carbon Nanotube Field Effect Transistor (CNFET) based Amplifiers", Global Research Collaboration (GRC) project, funded by Semiconductor Research Corporation, NC, USA (Principal Investigator).
  4. "Special Manpower Development Project in VLSI Design and related software (SMDP II)" at IIT Guwahati, Department of Information Technology, India (Investigator) (This is an Institute level project).
  5. "National MEMS Design Center at IIT Guwahati" under National Program on Micro and Smart Systems (NPMASS) (Principal Investigator) (This is an Institute level project).
  6. "Technology Incubation & Development of Entrepreneurs (TIDE) at IIT Guwahati in the areas of Electronics and ICT" Government of India a scheme by Ministry of Communications and Information technology by Department of Information Technology, India (Principal Investigator) (This is an Institute level project and presently the project is under Technology Incubation Centre, IIT Guwahati).
  7. "Digital VLSI Design Virtual Lab", Under the National Mission on Education through ICT (Principal Investigator) .
  8. "Design, Fabrication and Testing of a Low Power Analog Front-End Chip for heart rate Detection", Instrument Development Division, Department of Science and Technology, India (Principal Investigator).

Integrated Circuit (Chip) Development:

The following chip prototypes were completed:
  1. Chip 1

    Name of the chip - SANGAI
    Technical specification – 4 Multilayer Inductors, 2.4 GHz VCO, 4 bit flash ADC, NMOS based Amplifier for GHz operation
    Foundary - UMC L180 1P6M MM/RFCMOS process of United Microelectronics Corporation (UMC) through the mini@sic programme of Europractice IC Service.
    Silicon area -1525μm×1525μm
    Test report – Two structures of outer diameter 130 μm and 222 μm and width of 8 μm were tested. The four layer proposed structures with the outer diameter of 130 μm resulted in an inductance of 6.9 nH at 1 GHz with a peak quality factor of 6 at 2.1 GHz while the inductor with the outer diameter of 222 μm has an inductance of 27 nH at 1 GHz with a peak quality factor of 3 at 1.1 GHz. The multilayer pyramidal symmetric inductor was implemented in the LC tank of a 2.4 GHz voltage controlled oscillator. The measured phase noise of the VCO is -99 dBc/Hz at 100 KHz and 108 dBc/Hz at 1 MHz offset frequency with power consumption of 5 mW. The VCO was tuned with an inversion mode PMOS varactor and it operated from 2.441 to 2.557 GHz.

  2. Chip 2

    Name of the chip - IndiaChip-Analog 3
    Participating Institutes: Jadavpur University, Kolkata and IIT Guwahati
    Chip Integrator: IIT Guwahati
    Technical specification (Designs from IIT Guwahati)– 0.5 V 480 nW preamplifier, CMOS low power Precision temperature sensor, Inductive coupled Interchip transceiver
    Foundary - UMC L180 1P6M MM/RFCMOS process of United Microelectronics Corporation (UMC) through the mini@sic programme of Europractice IC Service.
    Silicon area -1525μm×1525μm>

Prototype Development:

The following product prototypes were completed:
  1. Prototype 1

    Title: "Fabrication and characterization of Carbon Nanotube Field Effect Transistors (CNFETs)"
    Name of Sponsor: Indian Nanoelectronics User Program (INUP) at Center of Excellence in Nanoelectronics (CEN) Indian Institute of Technology Bombay, India
    Investigators: Roy Paily and K.C. Narasimhamurthy
    Duration:12-01-2010 to 21-04-2010
    Project Details:Deposition of thin-film of SWCNT on the Hafnium oxide and SiO2 layers and achieved a good nanotube density. Fabricated semiconducting carbon nanotube thin-film transistors (SN-TFT) of channel dimensions from 2 µm to 500 µm. SN-TFTs of various gate structures like global back gate, local back gate, top gate and dual gate are fabricated. The SN-TFTs have exhibited excellent p-type output characteristics for various gate voltages. The devices have shown good subthreshold slope, on-off current ratio, transconductance and carrier mobility.

  2. Prototype 2

    Title: "High Aspect Ratio Structures Fabricated over SAW Resonator"
    Name of Sponsor: Indian Nanoelectronics User's Programme, Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science (IISc), Bangalore, India
    Investigators: N. Ramakrishnan, Harshal B. Nemade and Roy Paily Palathinkal
    Year: 2010
    Project Details: More than 150 SAW resonators were fabricated in three 4 inch lithium niobate wafers. SU-8 pillar structures were fabricated over the SAW patterns to study the mass loading characteristics of high aspect ratio structures. Recipe to fabricate high aspect ratio SU-8 structures on lithium niobate were identified during the project. Resonance frequency of each resonator with and without pillars was measured and the pillars dimensions were recorded using optical microscope and SEM.

  3. Prototype 3

    Title: "Design and Fabrication of a Glucose Sensor Based on Osmosis Principle"
    Name of Sponsor: Indian Nanoelectronics User's Programme, Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science (IISc), Bangalore, India
    Investigators: Nagesg CH and Roy Paily Palathinkal
    Year: 2013
    Project Details: Few Sensors based on osmosis principle were designed and fabricated for glucose sensing application. The advantages of sensors are their chemical free nature, better response time, improved life time and absence any mechanical excitations. The device was tested with different glucose concentrations ranging from 50 mg/dL to 450 mg/dL and the output voltage of the glucose sensor was increased from -6.7 mV to 22.4 mV

  4. Prototype 4

    Title: Development of PIN Photodiodes with Low Dark current for Scintillation Detection"
    Name of Sponsor: Defense Research and Development Organization, Hyderabad, India
    Duration: 02-02-1999 to 01-11-2001
    Principal Investigator: Dr. Amitava DasGupta, Professor, EE Dept., IIT Madras
    Involvement in the Project: Worked as a Senior Project Officer from 07-04-1999 till the completion of the project. The responsibilities include the design of the wafer, design and development of the mask for PIN Photodiodes and fabrication of the PIN diodes with low dark current. After successful completion of the project, complete process document and packaged PIN diodes suitable for scintillation detection were delivered to DRDL.

  5. Prototype 5

    Title: "Development of Silicon PIN Photodiodes for Detecting He-Ne Laser Signal"
    Name of Sponsor: ELOIRA, RCA, Hyderabad
    Principal Investigator: Dr. Amitava DasGupta, Professor, EE Dept., IIT Madras
    Duration:09-07-2001 to 31-05-2003
    Involvement in the Project: Worked as a Project Officer for the project. The responsibilities include the design of the wafer, design and development of the mask for PIN Photodiodes and fabrication of the PIN diodes with low dark current. The specifications were Dark current: < 1 nA at 12 V reverse bias, Responsivity: 0.40 A/W at 623 nm wavelength for devices with dimensions of 100 µm width and 60 µm separations. After successful completion of the project, complete process document and packaged PIN diodes suitable for scintillation detection were delivered to ELOIRA.

  6. Prototype 6

    Title: "Indigenous Development of Si PIN Photodiodes"
    Name of Sponsor: IISU, Indian Space Research Organization, Trivandrum, India
    Principal Investigator: Dr. Amitava DasGupta, Professor, EE Dept., IIT Madras
    Duration:16-04-2003 to 15-04-2004
    Involvement in the Project: Worked as a Project Officer for the project. The responsibilities include the design of the wafer, design and development of the mask for PIN Photodiodes and fabrication of the PIN diodes with low dark current. The specifications were Dark current: < 1 nA at 5 V reverse bias, Responsivity: 0.40 A/W at 623 nm wavelength for devices with dimensions of 200 µm width and 60 µm separations. The initial fabrication and packaging of devices were completed successfully completed by 2004 April end.