List of Publications

Book Chapter

  1. "Formal Modelling and Verification of Compensating Web Transactions"
    S. Das, S. Chakraborty, H. K. Kapoor and K. L. Man
    ITET, World Scientific, 2013.

  2. "Formal Verification and Synthesis of NULL Conventional Logic Circuits"
    H. K. Kapoor, J. Ma, T. Krilavicius, K. L. Man and C-U. Lei
    IAENG Transactions on Engineering Technologies, Volume 7,
    World Scientific, 2012.

Refereed Journal Articles

  1. "A Security Framework for NoC Using Authenticated Encryption and Session Keys"
    H. K. Kapoor, G. B. Rao, S. Arshi and G. Trivedi
    Journal of Circuits, Systems, and Signal Processing, Springer.
    18 pages. DOI 10.1007/s00034-013-9568-5

  2. "Design and Formal Verification of a Hierarchical Cache Coherence Protocol
    for NoC based Multiprocessors"
    H. K. Kapoor, P. Kanakala, M. Verma and S. Das
    Journal of Supercomputing, Springer. 26 pages. DOI 10.1007/s11227-012-0865-8

  3. "A Formal Framework for Interfacing Mixed-Timing Systems"
    S. Das, H. K. Kapoor and P. S. Duggirala
    Integration the VLSI Journal, Elsevier. 10 pages. DOI 10.1016/j.vlsi.2012.06.001

  4. "Formal Approach for DVS-based Power Management for Multiple Server
    System in Presence of Server Failure and Repair"
    L. Chandnani and H. K. Kapoor
    IEEE Transactions on Industrial Informatics, 9(1):502-513, Feb. 2013.

  5. "Model Checking of Independent Compensating Web-Transactions"
    H. K. Kapoor, S. Das, B. Raju and K. L. Man
    IAENG International Journal of Computer Science - IJCS, 2012.

  6. "Specification and Analysis of NCL Circuits"
    J. Ma, H.K. Kapoor, T. Krilavicius, K.L. Man, et. al
    Engineering Letters, 19(3):215-222, Sep 2011, IAENG

  7. "Handling Multiple Hotspots in Wormhole NoCs"
    H. K. Kapoor, S. Das and B. V. Balakrishna
    Indian Journal of VLSI and Electronic System Design (IJVED)

  8. "Process Algebraic View of Latency-Insensitive Systems"
    H. K. Kapoor
    IEEE Transactions on Computers, 58(7):931-944, July 2009

  9. "Controllable Delay-Insensitive Processes"
    M. B. Josephs and H. K. Kapoor
    Fundamenta Informaticae , 78(1):101-130, 2007, IOS Press

  10. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Fundamenta Informaticae, 70(1-2):21-48, March 2006, IOS Press

  11. "Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench"
    H. K. Kapoor and M. B. Josephs
    Information Processing Letters, 89(6):293-296, March 2004, Elsevier

Refereed Conference/Workshop Papers

    2012

  1. "Modelling and Verification of Compensating Transactions using the Spin Tool"
    K. Wan, H. K. Kapoor, S. Das, B. Raju, T. Krilavicius and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS)
    pp. 1163-1168, March 2012, Hong Kong. IAENG

    2. 2011

  2. "An Authenticated Encryption based Security Framework for NoC Architectures"
    H. K. Kapoor and K. Sajeesh
    Proc. of the International Symposium on Electronic System Design (ISED),
    pp. 134-139, Dec 2011, IEEE

  3. "Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips"
    K. L. Man, K. Yedluri, H. K. Kapoor, C-U Lei, E. G. Lima and J. Ma
    Proc. of the International Conference on Advances in Control Engineering and Information Science (CEIS),
    Volume 15, pp 3406-3410, Procedia Engineering, 2011, Elsevier

  4. "Performance Improvement by N-Chance Clustered Caching in NoC based Chip Multi-Processors"
    R. Yarlagadda, S. R. Kuppannagari and H. K. Kapoor
    Proc. of the International Conference on Computer Design (CDES)

  5. "Clustered Caching for Improving Performance and Energy requirements in NoC based Multiprocessors"
    H. K. Kapoor, L. Chatterjee and R. Yarlagadda
    Proc. of the International Conference on Computer Design (CDES)

  6. "Towards a Language Based Synthesis of NCL Circuits"
    H. K. Kapoor, A. Asthana, T. Krilavicius, W. Zeng, J. Ma and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS),
    pp. 1033-1038, March 2011, Hong Kong. IAENG (Certificate of Merit)

    7. 2010

  7. "Process Algebraic Specification of DI Circuits"
    K. L. Man, A. Asthana, H. K. Kapoor, T. Krilavicius and J. Chang
    Proc. of the 7th IEEE International SoC Design Conference (ISOCC), pp. 396-399, Nov 2010. Korea. IEEE

  8. "Interface Process Generation to Compose Delay-Insensitive Asynchronous Modules"
    H. K. Kapoor
    Proc. of the International Conference on Communication, Computers and Devices (ICCCD), India, 2010

  9. "Exploring use of NoC in Reconfigurable Video Coding"
    A. Patel and H. K. Kapoor
    Proc. of 23rd IEEE International Conference on VLSI Design, pp. 134-139, Jan 2010

    10. 2009

  10. "Mixed clock FIFO Design"
    R. Yarlagadda, J. Karthik and H. K. Kapoor
    Proc. of the 13th VLSI Design And Test Symposium (VDAT), Bangalore, India, 2009

    11. 2007

  11. "Modelling Latency-Insensitive Systems in CSP"
    H. K. Kapoor
    Proc. of the 7th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp 231-232, July 2007

    12. 2006

  12. "Formal Modelling and Verification of an Asynchronous DLX Pipeline"
    H. K. Kapoor
    Proc. of the 4th IEEE International Conference on Software Engineering and Formal Methods (SEFM), pp. 118-127, Sep 2006

    13. 2005

  13. "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation"
    H. K. Kapoor and M. B. Josephs
    Proc. of the 5th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 58-67, June 2005

    14. 2004

  14. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Proc. of the 4th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 89-98, June 2004

  15. "Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis"
    H. K. Kapoor and M. B. Josephs
    Proc. of 41st ACM Design Automation Conference (DAC), pp. 830-833, June 2004

    16. 2003

  16. "Computer-aided Synthesis and Verification of Delay-insensitive Protocols"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Demonstration at the University Booth of the DATE Conference, Germany, March 2003

  17. "Automated Transformation of Delay-Insensitive Sequential Processes"
    H. K. Kapoor and M. B. Josephs
    Poster in First EDAA Ph.D. Forum at the DATE Conference, Germany, March 2003

    18. 2002

  18. "Handshaking Expansion versus Delay-Insensitive Sequential Processes"
    H.K. Kapoor and M.B. Josephs
    in EPSRC PREP2002, Univeristy of Nottingham, April 2002


Ph.D. Thesis

  • H. K. Kapoor, "Delay Insensitive Processes: A Formal Approach to the Design of Asynchronous Circuits", July 2004. [abstract]