List of Publications

Refereed Journal Articles

  1. "Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets"
    S. Das and H. K. Kapoor
    IEEE Transaction on Parallel and Distributed Systems (TPDS), 2017.

  2. "Performance Linked Dynamic Cache Tuning: A Static Energy Reduction Approach in Tiled CMPs"
    S. Chakraborty and H. K. Kapoor
    Journal of Microprocessors and Microsystems, Elsevier, 2017.

  3. "A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture"
    S. Das and H. K. Kapoor
    ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016.

  4. "PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog"
    K. L. Man, C-U. Lei, H. K. Kapoor, T. Krilavicius, J. Ma and N. Zhang
    Computing and Informatics, 35(1):143-176, 2016.

  5. "A Discrete Event System Approach to Online Testing of Asynchronous Circuits"
    P. K. Biswal, K. Mishra, S. Biswas and H. K. Kapoor
    Journal of VLSI Design, 2015, Hindawi.

  6. "Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors"
    S. Das and H. K. Kapoor
    Journal of Microprocessors and Microsystems, 38(4):263-275, 2014. Elsevier.

  7. "A Security Framework for NoC Using Authenticated Encryption and Session Keys"
    H. K. Kapoor, G. B. Rao, S. Arshi and G. Trivedi
    Journal of Circuits, Systems, and Signal Processing, 32(6):2605-2622, 2013. Springer.

  8. "Design and Formal Verification of a Hierarchical Cache Coherence Protocol
    for NoC based Multiprocessors"
    H. K. Kapoor, P. Kanakala, M. Verma and S. Das
    Journal of Supercomputing, 65(2):771-796, August 2013. Springer.

  9. "A Formal Framework for Interfacing Mixed-Timing Systems"
    S. Das, H. K. Kapoor and P. S. Duggirala
    Integration the VLSI Journal, 46(3):255-264, June 2013. Elsevier.

  10. "Formal Approach for DVS-based Power Management for Multiple Server
    System in Presence of Server Failure and Repair"
    L. Chandnani and H. K. Kapoor
    IEEE Transactions on Industrial Informatics, 9(1):502-513, Feb. 2013.

  11. "Model Checking of Independent Compensating Web-Transactions"
    H. K. Kapoor, S. Das, B. Raju and K. L. Man
    IAENG International Journal of Computer Science - IJCS, 2012.

  12. "Specification and Analysis of NCL Circuits"
    J. Ma, H.K. Kapoor, T. Krilavicius, K.L. Man, et. al
    Engineering Letters, 19(3):215-222, Sep 2011, IAENG

  13. "Handling Multiple Hotspots in Wormhole NoCs"
    H. K. Kapoor, S. Das and B. V. Balakrishna
    Indian Journal of VLSI and Electronic System Design (IJVED)

  14. "Process Algebraic View of Latency-Insensitive Systems"
    H. K. Kapoor
    IEEE Transactions on Computers, 58(7):931-944, July 2009

  15. "Controllable Delay-Insensitive Processes"
    M. B. Josephs and H. K. Kapoor
    Fundamenta Informaticae , 78(1):101-130, 2007, IOS Press

  16. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Fundamenta Informaticae, 70(1-2):21-48, March 2006, IOS Press

  17. "Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench"
    H. K. Kapoor and M. B. Josephs
    Information Processing Letters, 89(6):293-296, March 2004, Elsevier

Refereed Conference/Workshop Papers

    2017

  1. "Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets"
    S. Agarwal and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, IEEE.

  2. "Latency Aware Block Replacement for L1 Caches in Chip MultiProcessors"
    S. Das and H. K. Kapoor
    IEEE Computer Society Annual Symposium on VLSI, (ISVLSI) 2017, IEEE.

  3. "Towards a better lifetime for Non-volatile caches in Chip Multiprocessors"
    S. Agarwal and H. K. Kapoor
    30th International Conference on VLSI Design (VLSID) 2017, IEEE.

  4. "Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors"
    S. Chakraborty and H. K. Kapoor
    30th International Conference on VLSI Design (VLSID) 2017, IEEE.

  5. 2016

  6. "Restricting Writes for Energy-efficient Hybrid Cache in Multi-core Architectures"
    S. Agarwal and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, IEEE.

  7. "Static Energy Reduction by Performance Linked Dynamic Cache Resizing"
    S. Chakraborty and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, IEEE.

  8. "Towards A Dynamic Associativity Enabled Write Prediction Based Hybrid Cache"
    S. Agarwal and H. K. Kapoor
    20th International Symposium on VLSI Design and Test (VDAT), 2016, IEEE Xplore.

  9. "Tag Only Storage for Capacity Optimised Last Level Cache in Chip Multiprocessors"
    S. Das, S. Das and H. K. Kapoor
    20th International Symposium on VLSI Design and Test (VDAT), 2016, IEEE Xplore.

  10. "Static Energy Efficient Cache Reconfiguration for Dynamic NUCA in Tiled CMPs"
    S. Chakraborty, S. Das and H. K. Kapoor
    31st ACM/SIGAPP Symposium On Applied Computing (SAC) 2016, ACM.

  11. "Dynamic Associativity Enabled DNUCA to Improve Block Localisation in Tiled CMPs"
    S. Das and H. K. Kapoor
    31st ACM/SIGAPP Symposium On Applied Computing (SAC) 2016, ACM.

  12. "Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches"
    S. Das and H. K. Kapoor
    29th International Conference on VLSI Design (VLSID) 2016, IEEE.

  13. 2015

  14. "An Efficient Searching Mechanism for Dynamic NUCA in Chip Multiprocessors"
    K. Vanapalli, H. K. Kapoor and S. Das
    19th International Symposium on VLSI Design and Test (VDAT), 2015, IEEE Xplore.

  15. "Power Aware Cache Miss Reduction by Energy Efficient Victim Retention"
    S. Chakraborty, S. Das and H. K. Kapoor
    19th International Symposium on VLSI Design and Test (VDAT), 2015, IEEE Xplore.

  16. "Performance constrained static energy reduction using way-sharing target-banks"
    S. Chakraborty, S. Das and H. K. Kapoor
    17th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM 2015)
    associated with IPDPS,
    2015, IEEE.

  17. "Static energy reduction by performance linked cache capacity management in Tiled CMPs"
    H. K. Kapoor, S. Das and S. Chakraborty
    30th ACM/SIGAPP Symposium On Applied Computing (SAC) 2015, ACM.

  18. "Dynamic Associativity Management using Utility Based Way-Sharing"
    S. Das and H. K. Kapoor
    30th ACM/SIGAPP Symposium On Applied Computing (SAC) 2015, ACM.

  19. "Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs"
    S. Das and H. K. Kapoor
    28th International Conference on VLSI Design (VLSID) 2015, IEEE.

  20. 2014

  21. "An Approach for Multicast Routing in Networks-on-Chip"
    M. LakshmiPrasad, S. Das and H. K. Kapoor
    13th International Conference on Information Technology (ICIT) 2014, IEEE.

  22. "RT-DVS for Power Optimization in Multiprocessor Real-time Systems"
    V. Naik, S. Das and H. K. Kapoor
    13th International Conference on Information Technology (ICIT) 2014, IEEE.

  23. "Modelling and Analysis of Wireless Communication over Networks-on-Chip"
    A. Kumar and H. K. Kapoor
    18th International Symposium on VLSI Design and Test (VDAT) 2014, IEEE Xplore.

  24. "A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip"
    N. K. Meena, H. K. Kapoor and S. Chakraborty
    18th International Symposium on VLSI Design and Test (VDAT) 2014, IEEE Xplore.

  25. "Cache Capacity and its Effects on Power Consumption for Tiled Chip Multi-Processors"
    S. Chakraborty, D. Deb, D. Buragohain and H. K. Kapoor
    International Conference on Electronics and Communication Systems (ICECS)
    2014, IEEE Xplore.

  26. "A Reduced Overhead Replacement Policy for Chip Multiprocessors having Victim Retention"
    S. Das, D. Buragohain and H. K. Kapoor
    International Conference on Electronics and Communication Systems (ICECS)
    2014, IEEE Xplore.

  27. 2013

  28. "Towards a Better Cache Utilization Using Controlled Cache Partitioning"
    P. D. Halwe, S. Das and H. K. Kapoor
    11th IEEE International Conference on Embedded Computing (EmbeddedCom2013), IEEE
    pp. 179-186, 2013, IEEE.

  29. "Dynamic Associativity Management using Fellow Sets"
    S. Das and H. K. Kapoor
    Proc. of the 4th International Symposium on Electronic System Design (ISED 2013), IEEE
    pp. 133-137, 2013, IEEE

  30. "Random-LRU: A Replacement Policy For Chip Multiprocessors"
    S. Das, P. Nagaraju, P. Halwe and H. K. Kapoor
    Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013),
    Communications in Computer and Information Science, vol. 382, pp. 204-213, Springer

  31. 2012

  32. "Modelling and Verification of Compensating Transactions using the Spin Tool"
    K. Wan, H. K. Kapoor, S. Das, B. Raju, T. Krilavicius and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS)
    pp. 1163-1168, March 2012, Hong Kong. IAENG

  33. 2011

  34. "An Authenticated Encryption based Security Framework for NoC Architectures"
    H. K. Kapoor and K. Sajeesh
    Proc. of the International Symposium on Electronic System Design (ISED),
    pp. 134-139, Dec 2011, IEEE

  35. "Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips"
    K. L. Man, K. Yedluri, H. K. Kapoor, C-U Lei, E. G. Lima and J. Ma
    Proc. of the International Conference on Advances in Control Engineering and Information Science (CEIS),
    Volume 15, pp 3406-3410, Procedia Engineering, 2011, Elsevier

  36. "Performance Improvement by N-Chance Clustered Caching in NoC based Chip Multi-Processors"
    R. Yarlagadda, S. R. Kuppannagari and H. K. Kapoor
    Proc. of the International Conference on Computer Design (CDES)

  37. "Clustered Caching for Improving Performance and Energy requirements in NoC based Multiprocessors"
    H. K. Kapoor, L. Chatterjee and R. Yarlagadda
    Proc. of the International Conference on Computer Design (CDES)

  38. "Towards a Language Based Synthesis of NCL Circuits"
    H. K. Kapoor, A. Asthana, T. Krilavicius, W. Zeng, J. Ma and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS),
    pp. 1033-1038, March 2011, Hong Kong. IAENG (Certificate of Merit)

  39. 2010

  40. "Process Algebraic Specification of DI Circuits"
    K. L. Man, A. Asthana, H. K. Kapoor, T. Krilavicius and J. Chang
    Proc. of the 7th IEEE International SoC Design Conference (ISOCC), pp. 396-399, Nov 2010. Korea. IEEE

  41. "Fair diagnosability in PN-based DES models"
    A. Khan, K. Misra, S. Biswas, J. Deka and H. K. Kapoor
    Proc. of the 8th IEEE International Conference on Control and Automation (ICCA), 2166 - 2171, 2010, IEEE.

  42. "Interface Process Generation to Compose Delay-Insensitive Asynchronous Modules"
    H. K. Kapoor
    Proc. of the International Conference on Communication, Computers and Devices (ICCCD), India, 2010

  43. "Exploring use of NoC in Reconfigurable Video Coding"
    A. Patel and H. K. Kapoor
    Proc. of 23rd IEEE International Conference on VLSI Design, pp. 134-139, Jan 2010

  44. 2009

  45. "Mixed clock FIFO Design"
    R. Yarlagadda, J. Karthik and H. K. Kapoor
    Proc. of the 13th VLSI Design And Test Symposium (VDAT), Bangalore, India, 2009

  46. 2007

  47. "Modelling Latency-Insensitive Systems in CSP"
    H. K. Kapoor
    Proc. of the 7th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp 231-232, July 2007

  48. 2006

  49. "Formal Modelling and Verification of an Asynchronous DLX Pipeline"
    H. K. Kapoor
    Proc. of the 4th IEEE International Conference on Software Engineering and Formal Methods (SEFM), pp. 118-127, Sep 2006

  50. 2005

  51. "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation"
    H. K. Kapoor and M. B. Josephs
    Proc. of the 5th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 58-67, June 2005

  52. 2004

  53. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Proc. of the 4th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 89-98, June 2004

  54. "Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis"
    H. K. Kapoor and M. B. Josephs
    Proc. of 41st ACM Design Automation Conference (DAC), pp. 830-833, June 2004

  55. 2003

  56. "Computer-aided Synthesis and Verification of Delay-insensitive Protocols"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Demonstration at the University Booth of the DATE Conference, Germany, March 2003

  57. "Automated Transformation of Delay-Insensitive Sequential Processes"
    H. K. Kapoor and M. B. Josephs
    Poster in First EDAA Ph.D. Forum at the DATE Conference, Germany, March 2003

  58. 2002

  59. "Handshaking Expansion versus Delay-Insensitive Sequential Processes"
    H.K. Kapoor and M.B. Josephs
    in EPSRC PREP2002, Univeristy of Nottingham, April 2002

Book Chapters

  1. "Formal Modelling and Verification of Compensating Web Transactions"
    S. Das, S. Chakraborty, H. K. Kapoor and K. L. Man
    ITET, World Scientific, 2013.

  2. "Formal Verification and Synthesis of NULL Conventional Logic Circuits"
    H. K. Kapoor, J. Ma, T. Krilavicius, K. L. Man and C-U. Lei
    IAENG Transactions on Engineering Technologies, Volume 7,
    World Scientific, 2012.

Ph.D. Thesis

  • H. K. Kapoor, "Delay Insensitive Processes: A Formal Approach to the Design of Asynchronous Circuits", July 2004. [abstract]