- S. Das, and H. K. Kapoor, “Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors,” Journal of Microprocessors and Microsystems (Elsevier). [accepted in Nov 2013].
- S. Das, P. S. Duggirala, and H. K. Kapoor, “A formal framework for interfacing mixed-timing systems,” Integration, the VLSI Journal (Elsevier), 2012.
[Online]. Available: http://www.sciencedirect.com/science/article/pii/S0167926012000363
- H. K. Kapoor, P. Kanakala, M. Verma, and S. Das, “Design and formal verification of a hierarchical cache coherence protocol for noc based multiprocessors,” The Journal of Supercomputing (Springer), 2012
[Online]. Available: http://www.springerlink.com/openurl.asp?genre=article&id=doi:10.1007/s11227-012-0865-8
- H. K. Kapoor, S. Das, B. Raju and K. L. Man, "Model Checking of Independent Compensating Web-Transactions", IAENG International Journal of Computer Science - IJCS, 2012.
- H. K. Kapoor, S. Das and B. V. Balakrishna “Handling Multiple Hotspots in Wormhole NoCs”, Indian Journal of VLSI and Electronic System Design (IJVED).
- S. Das, S. Chakraborty, H. K. Kapoor and K. L. Man, "Formal Modelling and Verification of Compensating Web Transactions" ITET, World Scientific, 2013.
- Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor, "Towards a Better Cache Utilization Using Controlled Cache Partitioning," 11th IEEE International Conference on Embedded Computing (EmbeddedCom2013), Chengdu, China. [paper accepted].
- S. Das and H. K. Kapoor, "Dynamic associativity management using fellow sets," 4th International Symposium on Electronic System Design (ISED 2013), NTU, Singapore [paper accepted].
- S. Das, N. Polavarapu, P. D. Halwe and H. K. Kapoor, "Random-LRU: A Replacement Policy For Chip Multiprocessors," 17th International Symposium on VLSI Design and Test (VDAT-2013), Jaipur, India.
- K. Wan, H. K. Kapoor, S. Das, B. Raju, T. Krilavicius and K. L. Man, “Modelling and Verification of Compensating Transactions using the Spin Tool”, Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS).March 2012, Hong Kong.
Under Review Papers
- “Formal Modeling of Mixed Clock FIFO to Build a Mixed Time Latency Insensitive System”, S. Das and H. K. Kapoor, Under Review, Paper submitted to Journal.