Invited Talk 1: Hardware Optimizations for Crypto Implementations (Speaker :Sandeep K. Shukla,IIT Kanpur)

 

Abstract: Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We consider three areas of crypto-engineering. They are building physical unclonable functions (PUFs), implementing encryption/decryption algorithms, and side channel proof crypto implementations. The techniques we employ range from area optimization through customized multiplexer design, fusing multiple operations into a single hardware element, folding and unrolling of iterative algorithms, creating reconfigurable implementations to achieve multiple operations with the same set of hardware elements, to techniques of obfuscation to defeat fault injection based attacks on the crypto implementation. While this paper describes the techniques, the implementation results are yet to be available, and will be presented at the conference.

 

Brief Bio of Sandeep K. Shukla:

Professor Sandeep K. Shukla received his bachelor degree in Computer Science and Engineering at Jadavpur University, Kolkata in 1991, his Masters and PhD degrees in Computer Science from the State University of New York at Albany, NY, USA in 1995 and 1997 respectively. He worked as a scientist at the GTE labs on telecommunications network management, distributed object technology, and event correlation technologies  between 1997 and1999. Between 1999 and 2001, he worked at the Intel Corporation on the formal verification of the ITANIUM processor, and on system level design languages. 2001-2002, he was a research faculty at the University of California at Irvine working on embedded system design. From 2002 till 2015, he has been an assistant, associate, and full professor at Virginia Tech, USA. He co-founded the Center for Embedded Systems for Critical Applications (CESCA) in 2007, and has been a director of the center between 2010 and 2012. The center grew to 9 tenure-track faculty, 60 graduate students and number of research faculty, and crossed the 2M dollar/year expenditure threshold during his directorship.  In 2015, he joined the Computer Science and Engineering Department of the Indian Institute of Technology Kanpur, India.  He received the prestigious Presidential Early Career Award for Scientists and Engineers (PECASE) from the White House in 2004, Frederich Wilhelm Bessel Award in 2008 from the Humboldt Foundation, Germany, Virginia Tech Faculty Fellow Award, A distinguished Alumni Award from the State University of New York at Albany, A best paper award at the Asia-Pacific Design Automation Conference, GTE Laboratories Excellence Award,ASEE/ONR Faculty Fellowship in 2005, ASEE/Air Force Senior Faculty Fellowship in 2007, and an Air Force Labs Faculty Fellowship in 2008. He has also been invited by the highly selective US National Academy of Engineering and US National Academy of Sciences Frontiers of Engineering and Frontiers of Science conferences.  He has been selected as an ACM Distinguished Scientist in 2013, and IEEE Fellow in 2014. He also served as ACM Distinguished Speaker between 2007 and 2015, IEEE Computer Society Distinguished Visitor between 2008 and 2012. Sandeep also has been a visiting faculty at INRIA, France, University of Kaiserslautern in Germany, MIT, and University of Birmingham UK for various periods of time.

He is currently the editor-in-chief of the ACM Transactions on Embedded Systems, Associate Editor of ACM Transactions on Cyber-Physical Systems, and Computing Reviews. In the past, he has been associate editors for IEEE Transactions on Computers, IEEE Transactions on Industrial Informatics, IEEE Design & Test, IEEE Embedded Systems Letters, and many other journals. He has guest-edited more than 15 special issues for various IEEE and ACM journals. He has written or edited 9 books, published over 200 journal and conference papers. He has been program chairs for 4 IEEE/ACM International conferences, and General Chair for 2 of these conferences. He has served on the program committee of more than 100 international conferences and workshops. He supervised 12 PhDs, and directed five post-doctoral scholars at Virginia Tech. He also supervised 10 Masters theses. He has been on examination committee for PhD and Habilitation theses in Sweden, Germany, France and  India.

Sandeep was elected an IEEE fellow for his contributions to applied probabilistic model checking for system design".  Sandeep s work on creating system level design languages with ability to express distinct models of computation for distinct parts of an embedded hardware/software system led to new kernels of SystemC language. His work on meta-modeling driven component composition pre-dated the standardization effort of the SPIRIT consortium. His novel interpretation of the clock calculus (which lies at the core of the compilation of  polychronous languages) as the problem of computing prime implicates in a propositional theory led to a new set of tools for multi-threaded code synthesis, and was  funded by US Air Force for an industrial implementation at L-3 Communications.  A new operational semantics for combining synchronous programming models within polychronous models that Sandeep and his colleagues recently published in the Science of Programming journal paved the way to combine the strengths of synchronous language based software synthesis and the asynchronous concurrency model of polychronous languages.   More recently, his group developed a number of co-simulation tools for data-communication enabled smart-grid, and a virtual SCADA system for industrial automation for the purpose of cyber-security threat modeling, simulation of cyber-attacks, and mitigation experimentation.   His main focus currently is cyber-security of cyber-physical systems, in particular, application of machine learning, and formal analysis to discover ways to distinguish physical dynamics variations due to stochastic variations, and cyber-attack induced variations.

 

Invited Talk 2:  Low power processors (Speaker: Prof. Masahiro Fujita, University of Tokyo)

Abstract:

 

 

 

 

Biography of Speaker: Dr. Fujita joined University of Tokyo in 2000. He has co-authored 2 books, and has over 150 publications. He has participated and chaired many prestigious conferences in CAD and VLSI designs. He has extensive high-level contacts in Japanese industry and academia. He has written over 100 technical papers on all aspects of logic design CAD. Dr. Fujita has received several awards from Japanese major scientific societies on his works in formal verification and logic synthesis. His doctor degree thesis was written in early 1980's and on model checking. Since then, he has been involved in many research projects on various aspects of formal verification. He has done innovative work in the areas of digital design verification at higher level design stages, hardware/software co-design and also digital/analog co-design, synthesis, and testing. Dr. Fujita received his Ph.D. degree in Information Engineering from the University of Tokyo.

 

Dr. Masahiro Fujita serves as Technical Advisor of Vennsa Technologies, Inc. Dr. Fujita has been Technical advisor at Real Intent, Inc. since January 2010. He served as Director of CAD in Fujitsu Laboratories of America, where he served for 15 years. From 1993 to 2000, he was assigned to Fujitsu's US research office and directed the CAD research group. Dr. Fujita has been a Member of Technical Advisory Board of Calypto Design Systems, K.K. since February 2005. He serves as a Member of the Advisory Board at Real Intent, Inc., and NextOp Software, Inc. He serves as Member of Technical Advisory Board of Calypto Design Systems, Inc. He serves as a Member of Technical Advisory Board of Atrenta Inc. Dr. Fujita serves as a Member of the Technical Advisory Board at Averant, Inc. He served as Member of Technical Advisory Board of Zenasis Technologies, Inc. Dr. Fujita has been Professor in the Department of Electronic Engineering in VLSI Design and Education Center (VDEC) of University of Tokyo since March 2000. in 1985.

 

 

Invited Talk 3:  PC to IoT : Technology Journey  (Speaker: Devesh Dwivedi, Deputy Director, Global Foundries, Bangalore)

 

 

Brief Biography of Speaker:

Dr. Devesh Dwivedi has ~20+  years of experience (~16+ years of industry + 4 years of research). He holds a Ph. D. degree in Electronics Engineering (Microelectronics) from IIT BHU. Since July 2015 he is working as Deputy Director, ASIC Product Engineering, GlobalFoundries, Bangalore.  Prior to this he worked  with System and Technology Group, IBM, 2008 to 2015. He worked on system-z, system-p and testsite projects. He was leading and managing custom IP (Memory, HSS &  Analog Mixed signal) design and development  at IBM India Pvt. Ltd, Bangalore, India. He started his carrier as SRAM circuit design engineer with ST Microelectronics in 1999. He has designed and developed several complex and state-of-the-art memories (custom as well compilable) for  ASIC OEMs and Server products.
Dr. Dwivedi has 10 granted/filled patents and 37 paper publications. He is member of technical review committees, patent and paper review board. He is examiner for graduate, post graduates and PhD thesis from Tier-1 technical institute and universities in India. He has delivered several invited talks at Institutes, Universities, National and International conferences. He also visiting professor at NIT & IIT, IEEE member.

 

 

 
Invited Talk 4: Petri-nets as Control Paths in Digital Systems Speaker: Prof. Madhav Desai, IIT Bombay
 
Abstract: Petri-nets provide a useful model for describing thebehaviour of discrete event systems. This behavioural description is often more convenient for expressing concurrency when compared to the alternative model of communicating state machines. 
However, in order to implement a Petri-net as a digital circuit, certain properties (liveness, safety) of the net need to be established. We introduce a class of Petri-nets which can be proved to be live and safe, and show that this class is powerful enough to describe 
control structures such as branching/looping, fork/join, and pipelines. The implementation of these nets using logic gates is also routine and standard techniques can be used to generate tests for such implementations. This approach has been used in practice in 
the AHIR-v2 toolset for digital design which has been developed at IIT-Bombay.

 

Brief Biography of Speaker:

Madhav P. Desai  is currently a professor in the department of Electrical Engineering at IIT Bombay. He received the B.Tech. in Electrical engineering from IIT Bombay in 1984, and the M. S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign. During the period 1992-1996, he worked in the Semiconductor Engineering Group at the Digital Equipment Corporation in Hudson, MA, where he was a Principal Engineer.

Dr. Desai's interests are in the areas of VLSI design and design tools, circuits and systems, and combinatorial algorithms. He has worked extensively on Static Timing Verification, Interconnect Optimization, Logic Synthesis, SRAM Design, and Circuit Optimization.  His doctoral work involved the study of the Simulated Annealing algorithm, which is a popular combinatorial optimization technique. While at Digital, he worked on timing verification, delay modeling, circuit and interconnect optimization and contributed to the design of two of the world's fastest CMOS microprocessors. He has been the recipient of GTE and Schlumberger Graduate Fellowships. He has served as a reviewer for the IEEE Transactions on Circuits and Systems, the IEEE Transactions on Computers, the SIAM Journal on Control, and various conferences.

 

 

 

Invited Talk 5: Scientific Computing: The Challenge for VLSI Design (Speaker: Sunil Sherlekar, Chairman & CEO, SankhyaSutra Labs. Pvt. Ltd., Banglore)

 

Abstract:The (increasing) challenge of scientific computing is characterised by one single problem. This problem is that of moving data around and manifests at all levels of the chip and computing hierarchy.The talk will describe the problem and indicate the research problems that need to be pursued to solve it.

 

Brief Biography of Speaker:

Sunil Sherlekar is the Chairman & CEO of Sankhyasutra Labs, a startup incubated in JNCASR Bangalore. Earlier he was Director of Parallel Computing Research at Intel Labs in Bangalore. Earlier he was the Founder & Head of Research at Tata Computational Research Labs in Pune (2006-2010), Head of Embedded Systems R&D at Tata Consultancy Services (2002-2006), CTO at Sasken Communication Technologies (1992-2002) and on the faculty of Computer Science & Engg. at IIT Bombay (1982-1992).   Sunil has a B. Tech. (Elect. Engg.) a M. Tech. (Computer Science & Engg.) and a Ph D. all from IIT Bombay. He has published several papers in the areas of Electronic Design Automation and VLSI Signal Processing and a book on VLSI Signal Processing. He was an Associate Editor of IEEE Trans on VLSI, on the Steering Committees of ASPDAC and International Conf on VLSI Design and on the Executive Committee of India Semiconductor Association.

Sunil s current areas of interest lie in mapping of HPC applications to architectures - many-core chips and clusters. Sunil is a Fellow of the Indian National Academy of Engineering and an Adjunct Professor at IIT Bombay.

Invited Talk 6: Real Time Face Recognition  on Massively Parallel Multi-core Architectures (Speaker: S. K. Nandy, IISc Bangalore)

 

Abstract: We present design and analysis of a scalable real-time Face Recognition (FR) module capable of performing 450 recognitions per second. We introduce an algorithm for FR, which is a combination of Weighted Modular Principle Component Analysis and Radial Basis Function Neural Networks. This algorithm offers better recognition accuracy in various practical conditions than algorithms used in existing architectures for real-time FR. To meet  real-time requirements, a Scalable Parallel Pipelined Architecture (SPPA) is developed by realizing the above FR algorithm as independent  parallel streams and sub-streams of computations. We cast the computations associated in the parallel streams in SPPA to Custom Function Units (as Compute Elements) in a massively parallel Coarse Grain Reconfigurable archetype like REDEFINE to achieve real-time face recognition.

 

Biography:

S. K. Nandy is a Professor in the Department of Computational and Data Sciences of the Indian Institute of Science, Bangalore. His research interests are in areas of High Performance Embedded Systems on a Chip, VLSI architectures for Reconfigurable Systems on Chip, and Architectures and Compiling Techniques for Heterogeneous Many Core  Systems.

Nandy received the B.Sc (Hons.) Physics degree from the Indian Institute  of Technology, Kharagpur, India, in 1977. He obtained the BE (Hons.) degree   in Electronics and Communication in 1980, MSc.(Engg.) degree in  Computer Science and Engineering in 1986, and the Ph.D. degree in  Computer Science and Engineering in 1989 from the Indian Institute of Science, Bangalore. He has over 170 publications in International Journals, and Proceedings of International Conferences, and 5 patents.